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File _service:tar_scm_kernel_repo:LoongArch-add-new-relocs-lsx-lasx-lvz-and-lbt.patch of Package binutils
From 2faa6acc123bf011f5eafd5f51803b9c2f2342e1 Mon Sep 17 00:00:00 2001 From: Peng Fan <fanpeng@loongson.cn> Date: Tue, 19 Sep 2023 09:18:16 +0800 Subject: [PATCH] LoongArch: add new relocs, lsx, lasx, lvz and lbt Signed-off-by: Peng Fan <fanpeng@loongson.cn> --- bfd/.gitignore | 1 + bfd/Makefile.am | 9 +- bfd/Makefile.in | 11 +- bfd/bfd-in2.h | 9 + bfd/bfd.c | 1 + bfd/coff-loongarch64.c | 169 ++ bfd/coffcode.h | 19 +- bfd/config.bfd | 2 +- bfd/configure | 1 + bfd/configure.ac | 1 + bfd/elfnn-loongarch.c | 711 +++++- bfd/elfxx-loongarch.c | 721 +++++-- bfd/elfxx-loongarch.h | 12 +- bfd/libbfd.h | 9 + bfd/libpei.h | 36 + bfd/peXXigen.c | 49 +- bfd/pei-loongarch64.c | 75 + bfd/peicode.h | 21 +- bfd/reloc.c | 25 + bfd/targets.c | 2 + binutils/readelf.c | 93 +- .../binutils-all/loongarch64/loongarch64.exp | 30 + .../loongarch64/pei-loongarch64.d | 15 + .../loongarch64/pei-loongarch64.s | 33 + binutils/testsuite/binutils-all/readelf.exp | 11 +- gas/config/loongarch-lex-wrapper.c | 2 +- gas/config/loongarch-parse.y | 20 + gas/config/tc-loongarch.c | 539 ++++- gas/config/tc-loongarch.h | 75 +- gas/ehopt.c | 2 +- gas/testsuite/gas/all/align.d | 5 +- gas/testsuite/gas/all/gas.exp | 10 +- gas/testsuite/gas/all/relax.d | 4 + gas/testsuite/gas/elf/dwarf2-11.d | 3 +- gas/testsuite/gas/elf/dwarf2-15.d | 3 +- gas/testsuite/gas/elf/dwarf2-16.d | 3 +- gas/testsuite/gas/elf/dwarf2-17.d | 3 +- gas/testsuite/gas/elf/dwarf2-18.d | 3 +- gas/testsuite/gas/elf/dwarf2-19.d | 3 +- gas/testsuite/gas/elf/dwarf2-5.d | 3 +- gas/testsuite/gas/elf/ehopt0.d | 3 + gas/testsuite/gas/elf/elf.exp | 3 + gas/testsuite/gas/elf/section11.d | 4 +- gas/testsuite/gas/lns/lns.exp | 1 + gas/testsuite/gas/loongarch/64_pcrel.d | 11 + gas/testsuite/gas/loongarch/64_pcrel.s | 2 + .../gas/loongarch/deprecated_reg_aliases.d | 18 + .../gas/loongarch/deprecated_reg_aliases.l | 7 + .../gas/loongarch/deprecated_reg_aliases.s | 5 + gas/testsuite/gas/loongarch/float_op.d | 4 +- gas/testsuite/gas/loongarch/float_op.s | 4 +- gas/testsuite/gas/loongarch/imm_ins.d | 80 + gas/testsuite/gas/loongarch/imm_ins.s | 83 + gas/testsuite/gas/loongarch/imm_ins_32.d | 57 + gas/testsuite/gas/loongarch/imm_ins_32.s | 60 + .../gas/loongarch/imm_ins_label-fail.d | 3 + .../gas/loongarch/imm_ins_label-fail.l | 3 + .../gas/loongarch/imm_ins_label-fail.s | 3 + gas/testsuite/gas/loongarch/imm_op.d | 44 +- gas/testsuite/gas/loongarch/jmp_op.d | 64 +- gas/testsuite/gas/loongarch/jmp_op.s | 1 + gas/testsuite/gas/loongarch/li.d | 23 + gas/testsuite/gas/loongarch/li.s | 22 + gas/testsuite/gas/loongarch/load_store_op.d | 80 +- gas/testsuite/gas/loongarch/loongarch.exp | 2 +- gas/testsuite/gas/loongarch/lvz-lbt.d | 191 ++ gas/testsuite/gas/loongarch/lvz-lbt.s | 181 ++ gas/testsuite/gas/loongarch/macro_op.d | 68 +- gas/testsuite/gas/loongarch/macro_op_32.d | 42 +- .../gas/loongarch/macro_op_large_abs.d | 138 +- .../gas/loongarch/macro_op_large_pc.d | 138 +- gas/testsuite/gas/loongarch/nop.d | 2 +- gas/testsuite/gas/loongarch/pcrel_norelax.d | 56 + gas/testsuite/gas/loongarch/pcrel_norelax.s | 42 + gas/testsuite/gas/loongarch/pcrel_relax.d | 60 + gas/testsuite/gas/loongarch/pcrel_relax.s | 46 + gas/testsuite/gas/loongarch/privilege_op.d | 8 +- gas/testsuite/gas/loongarch/raw-insn.d | 11 + gas/testsuite/gas/loongarch/raw-insn.s | 7 + gas/testsuite/gas/loongarch/relax_align.d | 26 + gas/testsuite/gas/loongarch/relax_align.s | 5 + gas/testsuite/gas/loongarch/reloc.d | 2 +- gas/testsuite/gas/loongarch/uleb128.d | 36 + gas/testsuite/gas/loongarch/uleb128.s | 20 + gas/testsuite/gas/loongarch/vector.d | 1461 +++++++++++++ gas/testsuite/gas/loongarch/vector.s | 1451 +++++++++++++ gas/testsuite/lib/gas-defs.exp | 3 - include/coff/loongarch64.h | 61 + include/coff/pe.h | 1 + include/elf/loongarch.h | 22 + include/opcode/loongarch.h | 22 +- ld/emultempl/loongarchelf.em | 3 + ld/testsuite/ld-elf/compressed1d.d | 3 + ld/testsuite/ld-elf/pr26936.d | 4 +- ld/testsuite/ld-elf/shared.exp | 3 +- ld/testsuite/ld-loongarch-elf/64_pcrel.d | 4 + ld/testsuite/ld-loongarch-elf/64_pcrel.s | 11 + ld/testsuite/ld-loongarch-elf/cmodel.exp | 29 +- ld/testsuite/ld-loongarch-elf/disas-jirl-32.d | 2 + ld/testsuite/ld-loongarch-elf/disas-jirl.d | 4 +- ld/testsuite/ld-loongarch-elf/ifunc.exp | 2 +- ld/testsuite/ld-loongarch-elf/jmp_op.d | 62 +- ld/testsuite/ld-loongarch-elf/jmp_op.s | 1 + .../ld-loongarch-elf/ld-loongarch-elf.exp | 18 +- .../ld-loongarch-elf/local-ifunc-reloc.d | 4 +- ld/testsuite/ld-loongarch-elf/macro_op.d | 162 +- ld/testsuite/ld-loongarch-elf/macro_op_32.d | 42 +- ld/testsuite/ld-loongarch-elf/pic.exp | 2 +- ld/testsuite/ld-loongarch-elf/relax-align.dd | 7 + ld/testsuite/ld-loongarch-elf/relax-align.s | 9 + ld/testsuite/ld-loongarch-elf/relax.exp | 77 + ld/testsuite/ld-loongarch-elf/relax.s | 16 + ld/testsuite/ld-loongarch-elf/uleb128.dd | 10 + ld/testsuite/ld-loongarch-elf/uleb128.s | 21 + opcodes/loongarch-dis.c | 150 +- opcodes/loongarch-opc.c | 1907 ++++++++++++++++- 116 files changed, 8912 insertions(+), 1072 deletions(-) create mode 100644 bfd/coff-loongarch64.c create mode 100644 bfd/pei-loongarch64.c create mode 100644 binutils/testsuite/binutils-all/loongarch64/loongarch64.exp create mode 100644 binutils/testsuite/binutils-all/loongarch64/pei-loongarch64.d create mode 100644 binutils/testsuite/binutils-all/loongarch64/pei-loongarch64.s create mode 100644 gas/testsuite/gas/loongarch/64_pcrel.d create mode 100644 gas/testsuite/gas/loongarch/64_pcrel.s create mode 100644 gas/testsuite/gas/loongarch/deprecated_reg_aliases.d create mode 100644 gas/testsuite/gas/loongarch/deprecated_reg_aliases.l create mode 100644 gas/testsuite/gas/loongarch/deprecated_reg_aliases.s create mode 100644 gas/testsuite/gas/loongarch/imm_ins.d create mode 100644 gas/testsuite/gas/loongarch/imm_ins.s create mode 100644 gas/testsuite/gas/loongarch/imm_ins_32.d create mode 100644 gas/testsuite/gas/loongarch/imm_ins_32.s create mode 100644 gas/testsuite/gas/loongarch/imm_ins_label-fail.d create mode 100644 gas/testsuite/gas/loongarch/imm_ins_label-fail.l create mode 100644 gas/testsuite/gas/loongarch/imm_ins_label-fail.s create mode 100644 gas/testsuite/gas/loongarch/li.d create mode 100644 gas/testsuite/gas/loongarch/li.s create mode 100644 gas/testsuite/gas/loongarch/lvz-lbt.d create mode 100644 gas/testsuite/gas/loongarch/lvz-lbt.s create mode 100644 gas/testsuite/gas/loongarch/pcrel_norelax.d create mode 100644 gas/testsuite/gas/loongarch/pcrel_norelax.s create mode 100644 gas/testsuite/gas/loongarch/pcrel_relax.d create mode 100644 gas/testsuite/gas/loongarch/pcrel_relax.s create mode 100644 gas/testsuite/gas/loongarch/raw-insn.d create mode 100644 gas/testsuite/gas/loongarch/raw-insn.s create mode 100644 gas/testsuite/gas/loongarch/relax_align.d create mode 100644 gas/testsuite/gas/loongarch/relax_align.s create mode 100644 gas/testsuite/gas/loongarch/uleb128.d create mode 100644 gas/testsuite/gas/loongarch/uleb128.s create mode 100644 gas/testsuite/gas/loongarch/vector.d create mode 100644 gas/testsuite/gas/loongarch/vector.s create mode 100644 include/coff/loongarch64.h create mode 100644 ld/testsuite/ld-loongarch-elf/64_pcrel.d create mode 100644 ld/testsuite/ld-loongarch-elf/64_pcrel.s create mode 100644 ld/testsuite/ld-loongarch-elf/relax-align.dd create mode 100644 ld/testsuite/ld-loongarch-elf/relax-align.s create mode 100644 ld/testsuite/ld-loongarch-elf/relax.exp create mode 100644 ld/testsuite/ld-loongarch-elf/relax.s create mode 100644 ld/testsuite/ld-loongarch-elf/uleb128.dd create mode 100644 ld/testsuite/ld-loongarch-elf/uleb128.s diff --git a/bfd/.gitignore b/bfd/.gitignore index d4f74231..36af6c33 100644 --- a/bfd/.gitignore +++ b/bfd/.gitignore @@ -11,6 +11,7 @@ /pepigen.c /pex64igen.c /pe-aarch64igen.c +/pe-loongarch64igen.c /stmp-bfd-h /targmatch.h diff --git a/bfd/Makefile.am b/bfd/Makefile.am index 376d54ae..eba97a78 100644 --- a/bfd/Makefile.am +++ b/bfd/Makefile.am @@ -573,9 +573,11 @@ BFD64_BACKENDS = \ mach-o-x86-64.lo \ mmo.lo \ pe-aarch64igen.lo \ + pe-loongarch64igen.lo \ pe-x86_64.lo \ pei-aarch64.lo \ pei-ia64.lo \ + pei-loongarch64.lo \ pei-x86_64.lo \ pepigen.lo \ pex64igen.lo \ @@ -617,6 +619,7 @@ BFD64_BACKENDS_CFILES = \ pe-x86_64.c \ pei-aarch64.c \ pei-ia64.c \ + pei-loongarch64.c \ pei-x86_64.c \ vms-alpha.c @@ -676,7 +679,7 @@ BUILD_CFILES = \ elf32-ia64.c elf64-ia64.c \ elf32-loongarch.c elf64-loongarch.c \ elf32-riscv.c elf64-riscv.c \ - peigen.c pepigen.c pex64igen.c pe-aarch64igen.c + peigen.c pepigen.c pex64igen.c pe-aarch64igen.c pe-loongarch64igen.c CFILES = $(SOURCE_CFILES) $(BUILD_CFILES) @@ -893,6 +896,10 @@ pe-aarch64igen.c: peXXigen.c echo "#line 1 \"peXXigen.c\"" > $@ $(SED) -e s/XX/peAArch64/g < $< >> $@ +pe-loongarch64igen.c: peXXigen.c + echo "#line 1 \"peXXigen.c\"" > $@ + $(SED) -e s/XX/peLoongArch64/g < $< >> $@ + host-aout.lo: Makefile # The following program can be used to generate a simple config file diff --git a/bfd/Makefile.in b/bfd/Makefile.in index 809ea2fd..66f4fde4 100644 --- a/bfd/Makefile.in +++ b/bfd/Makefile.in @@ -1000,9 +1000,11 @@ BFD64_BACKENDS = \ mach-o-x86-64.lo \ mmo.lo \ pe-aarch64igen.lo \ + pe-loongarch64igen.lo \ pe-x86_64.lo \ pei-aarch64.lo \ pei-ia64.lo \ + pei-loongarch64.lo \ pei-x86_64.lo \ pepigen.lo \ pex64igen.lo \ @@ -1044,6 +1046,7 @@ BFD64_BACKENDS_CFILES = \ pe-x86_64.c \ pei-aarch64.c \ pei-ia64.c \ + pei-loongarch64.c \ pei-x86_64.c \ vms-alpha.c @@ -1102,7 +1105,7 @@ BUILD_CFILES = \ elf32-ia64.c elf64-ia64.c \ elf32-loongarch.c elf64-loongarch.c \ elf32-riscv.c elf64-riscv.c \ - peigen.c pepigen.c pex64igen.c pe-aarch64igen.c + peigen.c pepigen.c pex64igen.c pe-aarch64igen.c pe-loongarch64igen.c CFILES = $(SOURCE_CFILES) $(BUILD_CFILES) SOURCE_HFILES = \ @@ -1555,6 +1558,7 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pe-arm-wince.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pe-arm.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pe-i386.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pe-loongarch64igen.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pe-mcore.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pe-sh.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pe-x86_64.Plo@am__quote@ @@ -1564,6 +1568,7 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pei-arm.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pei-i386.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pei-ia64.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pei-loongarch64.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pei-mcore.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pei-sh.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pei-x86_64.Plo@am__quote@ @@ -2026,6 +2031,10 @@ pe-aarch64igen.c: peXXigen.c echo "#line 1 \"peXXigen.c\"" > $@ $(SED) -e s/XX/peAArch64/g < $< >> $@ +pe-loongarch64igen.c: peXXigen.c + echo "#line 1 \"peXXigen.c\"" > $@ + $(SED) -e s/XX/peLoongArch64/g < $< >> $@ + host-aout.lo: Makefile # The following program can be used to generate a simple config file diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h index c8761a61..5e4ad98d 100644 --- a/bfd/bfd-in2.h +++ b/bfd/bfd-in2.h @@ -6343,6 +6343,15 @@ assembler and not (currently) written to any object files. */ BFD_RELOC_LARCH_TLS_GD_HI20, BFD_RELOC_LARCH_32_PCREL, BFD_RELOC_LARCH_RELAX, + BFD_RELOC_LARCH_DELETE, + BFD_RELOC_LARCH_ALIGN, + BFD_RELOC_LARCH_PCREL20_S2, + BFD_RELOC_LARCH_CFA, + BFD_RELOC_LARCH_ADD6, + BFD_RELOC_LARCH_SUB6, + BFD_RELOC_LARCH_ADD_ULEB128, + BFD_RELOC_LARCH_SUB_ULEB128, + BFD_RELOC_LARCH_64_PCREL, BFD_RELOC_UNUSED }; typedef enum bfd_reloc_code_real bfd_reloc_code_real_type; diff --git a/bfd/bfd.c b/bfd/bfd.c index 1d6af967..fade8042 100644 --- a/bfd/bfd.c +++ b/bfd/bfd.c @@ -1738,6 +1738,7 @@ bfd_get_sign_extend_vma (bfd *abfd) || strcmp (name, "pei-aarch64-little") == 0 || strcmp (name, "pe-arm-wince-little") == 0 || strcmp (name, "pei-arm-wince-little") == 0 + || strcmp (name, "pei-loongarch64") == 0 || strcmp (name, "aixcoff-rs6000") == 0 || strcmp (name, "aix5coff64-rs6000") == 0) return 1; diff --git a/bfd/coff-loongarch64.c b/bfd/coff-loongarch64.c new file mode 100644 index 00000000..f752efbb --- /dev/null +++ b/bfd/coff-loongarch64.c @@ -0,0 +1,169 @@ +/* BFD back-end for LoongArch64 COFF files. + Copyright (C) 2022 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + + +#ifndef COFF_WITH_peLoongArch64 +#define COFF_WITH_peLoongArch64 +#endif + +/* Note we have to make sure not to include headers twice. + Not all headers are wrapped in #ifdef guards, so we define + PEI_HEADERS to prevent double including here. */ +#ifndef PEI_HEADERS +#include "sysdep.h" +#include "bfd.h" +#include "libbfd.h" +#include "coff/loongarch64.h" +#include "coff/internal.h" +#include "coff/pe.h" +#include "libcoff.h" +#include "libiberty.h" +#endif + +#include "libcoff.h" + +/* The page size is a guess based on ELF. */ + +#define COFF_PAGE_SIZE 0x4000 + +/* All users of this file have bfd_octets_per_byte (abfd, sec) == 1. */ +#define OCTETS_PER_BYTE(ABFD, SEC) 1 + +#ifndef PCRELOFFSET +#define PCRELOFFSET true +#endif + +/* Currently we don't handle any relocations. */ +static reloc_howto_type pe_loongarch64_std_reloc_howto[] = + { + + }; + +#define COFF_DEFAULT_SECTION_ALIGNMENT_POWER 2 + +#ifndef NUM_ELEM +#define NUM_ELEM(a) ((sizeof (a)) / sizeof ((a)[0])) +#endif + +#define NUM_RELOCS NUM_ELEM (pe_loongarch64_std_reloc_howto) + +#define RTYPE2HOWTO(cache_ptr, dst) \ + (cache_ptr)->howto = NULL + +#ifndef bfd_pe_print_pdata +#define bfd_pe_print_pdata NULL +#endif + +/* Handle include/coff/loongarch64.h external_reloc. */ +#define SWAP_IN_RELOC_OFFSET H_GET_32 +#define SWAP_OUT_RELOC_OFFSET H_PUT_32 + +/* Return TRUE if this relocation should + appear in the output .reloc section. */ + +static bool +in_reloc_p (bfd * abfd ATTRIBUTE_UNUSED, + reloc_howto_type * howto) +{ + return !howto->pc_relative; +} + +#include "coffcode.h" + +/* Target vectors. */ +const bfd_target +#ifdef TARGET_SYM + TARGET_SYM = +#else + loongarch64_pei_vec = +#endif +{ +#ifdef TARGET_NAME + TARGET_NAME, +#else + "pei-loongarch64", /* Name. */ +#endif + bfd_target_coff_flavour, + BFD_ENDIAN_LITTLE, /* Data byte order is little. */ + BFD_ENDIAN_LITTLE, /* Header byte order is little. */ + + (HAS_RELOC | EXEC_P /* Object flags. */ + | HAS_LINENO | HAS_DEBUG + | HAS_SYMS | HAS_LOCALS | WP_TEXT | D_PAGED | BFD_COMPRESS | BFD_DECOMPRESS), + + (SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD | SEC_RELOC /* Section flags. */ +#if defined(COFF_WITH_PE) + | SEC_LINK_ONCE | SEC_LINK_DUPLICATES | SEC_READONLY | SEC_DEBUGGING +#endif + | SEC_CODE | SEC_DATA | SEC_EXCLUDE ), + +#ifdef TARGET_UNDERSCORE + TARGET_UNDERSCORE, /* Leading underscore. */ +#else + 0, /* Leading underscore. */ +#endif + '/', /* Ar_pad_char. */ + 15, /* Ar_max_namelen. */ + 0, /* match priority. */ + TARGET_KEEP_UNUSED_SECTION_SYMBOLS, /* keep unused section symbols. */ + + /* Data conversion functions. */ + bfd_getl64, bfd_getl_signed_64, bfd_putl64, + bfd_getl32, bfd_getl_signed_32, bfd_putl32, + bfd_getl16, bfd_getl_signed_16, bfd_putl16, /* Data. */ + /* Header conversion functions. */ + bfd_getl64, bfd_getl_signed_64, bfd_putl64, + bfd_getl32, bfd_getl_signed_32, bfd_putl32, + bfd_getl16, bfd_getl_signed_16, bfd_putl16, /* Hdrs. */ + + /* Note that we allow an object file to be treated as a core file as well. */ + { /* bfd_check_format. */ + _bfd_dummy_target, + coff_object_p, + bfd_generic_archive_p, + coff_object_p + }, + { /* bfd_set_format. */ + _bfd_bool_bfd_false_error, + coff_mkobject, + _bfd_generic_mkarchive, + _bfd_bool_bfd_false_error + }, + { /* bfd_write_contents. */ + _bfd_bool_bfd_false_error, + coff_write_object_contents, + _bfd_write_archive_contents, + _bfd_bool_bfd_false_error + }, + + BFD_JUMP_TABLE_GENERIC (coff), + BFD_JUMP_TABLE_COPY (coff), + BFD_JUMP_TABLE_CORE (_bfd_nocore), + BFD_JUMP_TABLE_ARCHIVE (_bfd_archive_coff), + BFD_JUMP_TABLE_SYMBOLS (coff), + BFD_JUMP_TABLE_RELOCS (coff), + BFD_JUMP_TABLE_WRITE (coff), + BFD_JUMP_TABLE_LINK (coff), + BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic), + + NULL, + + COFF_SWAP_TABLE +}; diff --git a/bfd/coffcode.h b/bfd/coffcode.h index d222c88d..e5b77099 100644 --- a/bfd/coffcode.h +++ b/bfd/coffcode.h @@ -2221,6 +2221,12 @@ coff_set_arch_mach_hook (bfd *abfd, void * filehdr) machine = internal_f->f_flags & F_AARCH64_ARCHITECTURE_MASK; break; #endif +#ifdef LOONGARCH64MAGIC + case LOONGARCH64MAGIC: + arch = bfd_arch_loongarch; + machine = internal_f->f_flags & F_LOONGARCH64_ARCHITECTURE_MASK; + break; +#endif #ifdef Z80MAGIC case Z80MAGIC: arch = bfd_arch_z80; @@ -2783,6 +2789,12 @@ coff_set_flags (bfd * abfd, return true; #endif +#ifdef LOONGARCH64MAGIC + case bfd_arch_loongarch: + * magicp = LOONGARCH64MAGIC; + return true; +#endif + #ifdef ARMMAGIC case bfd_arch_arm: #ifdef ARM_WINCE @@ -3877,7 +3889,7 @@ coff_write_object_contents (bfd * abfd) internal_f.f_flags |= IMAGE_FILE_LARGE_ADDRESS_AWARE; #endif -#if !defined(COFF_WITH_pex64) && !defined(COFF_WITH_peAArch64) +#if !defined(COFF_WITH_pex64) && !defined(COFF_WITH_peAArch64) && !defined(COFF_WITH_peLoongArch64) #ifdef COFF_WITH_PE internal_f.f_flags |= IMAGE_FILE_32BIT_MACHINE; #else @@ -3931,6 +3943,11 @@ coff_write_object_contents (bfd * abfd) internal_a.magic = ZMAGIC; #endif +#if defined(LOONGARCH64) +#define __A_MAGIC_SET__ + internal_a.magic = ZMAGIC; +#endif + #if defined MCORE_PE #define __A_MAGIC_SET__ internal_a.magic = IMAGE_NT_OPTIONAL_HDR_MAGIC; diff --git a/bfd/config.bfd b/bfd/config.bfd index 34b318f4..b21594b9 100644 --- a/bfd/config.bfd +++ b/bfd/config.bfd @@ -1423,7 +1423,7 @@ case "${targ}" in loongarch64-*) targ_defvec=loongarch_elf64_vec - targ_selvecs="loongarch_elf32_vec loongarch_elf64_vec" + targ_selvecs="loongarch_elf32_vec loongarch_elf64_vec loongarch64_pei_vec" want64=true ;; #endif diff --git a/bfd/configure b/bfd/configure index 1adac005..3d18b31a 100755 --- a/bfd/configure +++ b/bfd/configure @@ -13375,6 +13375,7 @@ do lm32_elf32_fdpic_vec) tb="$tb elf32-lm32.lo elf32.lo $elf" ;; loongarch_elf32_vec) tb="$tb elf32-loongarch.lo elfxx-loongarch.lo elf32.lo elf-ifunc.lo $elf" ;; loongarch_elf64_vec) tb="$tb elf64-loongarch.lo elf64.lo elfxx-loongarch.lo elf32.lo elf-ifunc.lo $elf"; target_size=64 ;; + loongarch64_pei_vec) tb="$tb pei-loongarch64.lo pe-loongarch64igen.lo $coff"; target_size=64 ;; m32c_elf32_vec) tb="$tb elf32-m32c.lo elf32.lo $elf" ;; m32r_elf32_vec) tb="$tb elf32-m32r.lo elf32.lo $elf" ;; m32r_elf32_le_vec) tb="$tb elf32-m32r.lo elf32.lo $elf" ;; diff --git a/bfd/configure.ac b/bfd/configure.ac index e5b67313..7d8faa1f 100644 --- a/bfd/configure.ac +++ b/bfd/configure.ac @@ -531,6 +531,7 @@ do lm32_elf32_fdpic_vec) tb="$tb elf32-lm32.lo elf32.lo $elf" ;; loongarch_elf32_vec) tb="$tb elf32-loongarch.lo elfxx-loongarch.lo elf32.lo elf-ifunc.lo $elf" ;; loongarch_elf64_vec) tb="$tb elf64-loongarch.lo elf64.lo elfxx-loongarch.lo elf32.lo elf-ifunc.lo $elf"; target_size=64 ;; + loongarch64_pei_vec) tb="$tb pei-loongarch64.lo pe-loongarch64igen.lo $coff"; target_size=64 ;; m32c_elf32_vec) tb="$tb elf32-m32c.lo elf32.lo $elf" ;; m32r_elf32_vec) tb="$tb elf32-m32r.lo elf32.lo $elf" ;; m32r_elf32_le_vec) tb="$tb elf32-m32r.lo elf32.lo $elf" ;; diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c index a623aa32..a418969a 100644 --- a/bfd/elfnn-loongarch.c +++ b/bfd/elfnn-loongarch.c @@ -27,6 +27,7 @@ #include "objalloc.h" #include "elf/loongarch.h" #include "elfxx-loongarch.h" +#include "opcode/loongarch.h" static bool loongarch_info_to_howto_rela (bfd *abfd, arelent *cache_ptr, @@ -93,6 +94,10 @@ struct loongarch_elf_link_hash_table /* The max alignment of output sections. */ bfd_vma max_alignment; + + /* The data segment phase, don't relax the section + when it is exp_seg_relro_adjust. */ + int *data_segment_phase; }; /* Get the LoongArch ELF linker hash table from a link_info structure. */ @@ -772,8 +777,8 @@ loongarch_elf_check_relocs (bfd *abfd, struct bfd_link_info *info, break; - case R_LARCH_B21: case R_LARCH_B16: + case R_LARCH_B21: case R_LARCH_B26: if (h != NULL) { @@ -972,15 +977,19 @@ loongarch_elf_adjust_dynamic_symbol (struct bfd_link_info *info, /* Make sure we know what is going on here. */ BFD_ASSERT (dynobj != NULL - && (h->needs_plt || h->type == STT_GNU_IFUNC || h->is_weakalias - || (h->def_dynamic && h->ref_regular && !h->def_regular))); + && (h->needs_plt + || h->type == STT_GNU_IFUNC + || h->is_weakalias + || (h->def_dynamic + && h->ref_regular + && !h->def_regular))); /* If this is a function, put it in the procedure linkage table. We will fill in the contents of the procedure linkage table later (although we could actually do it here). */ if (h->type == STT_FUNC || h->type == STT_GNU_IFUNC || h->needs_plt) { - if (h->plt.refcount < 0 + if (h->plt.refcount <= 0 || (h->type != STT_GNU_IFUNC && (SYMBOL_REFERENCES_LOCAL (info, h) || (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT @@ -993,8 +1002,6 @@ loongarch_elf_adjust_dynamic_symbol (struct bfd_link_info *info, h->plt.offset = MINUS_ONE; h->needs_plt = 0; } - else - h->needs_plt = 1; return true; } @@ -1533,7 +1540,7 @@ elfNN_allocate_ifunc_dynrelocs (struct elf_link_hash_entry *h, void *inf) /* Allocate space in .plt, .got and associated reloc sections for ifunc dynamic relocs. */ -static bool +static int elfNN_allocate_local_ifunc_dynrelocs (void **slot, void *inf) { struct elf_link_hash_entry *h = (struct elf_link_hash_entry *) *slot; @@ -1695,7 +1702,7 @@ loongarch_elf_size_dynamic_sections (bfd *output_bfd, /* Allocate .plt and .got entries, and space for local ifunc symbols. */ htab_traverse (htab->loc_hash_table, - (void *) elfNN_allocate_local_ifunc_dynrelocs, info); + elfNN_allocate_local_ifunc_dynrelocs, info); /* Don't allocate .got.plt section if there are no PLT. */ if (htab->elf.sgotplt && htab->elf.sgotplt->size == GOTPLT_HEADER_SIZE @@ -1888,7 +1895,7 @@ loongarch_reloc_rewrite_imm_insn (const Elf_Internal_Rela *rel, int bits = bfd_get_reloc_size (howto) * 8; uint32_t insn = bfd_get (bits, input_bfd, contents + rel->r_offset); - if (!loongarch_adjust_reloc_bitsfield(howto, &reloc_val)) + if (!loongarch_adjust_reloc_bitsfield (input_bfd, howto, &reloc_val)) return bfd_reloc_overflow; insn = (insn & (uint32_t)howto->src_mask) @@ -2008,42 +2015,74 @@ perform_relocation (const Elf_Internal_Rela *rel, asection *input_section, bfd_put (bits, input_bfd, value, contents + rel->r_offset); break; + /* LoongArch only has add/sub reloc pair, not has set/sub reloc pair. + Because set/sub reloc pair not support multi-thread. While add/sub + reloc pair process order not affect the final result. + + For add/sub reloc, the original value will be involved in the + calculation. In order not to add/sub extra value, we write 0 to symbol + address at assembly time. + + add/sub reloc bits determined by the value after symbol subtraction, + not symbol value. + + add/sub reloc save part of the symbol value, so we only need to + save howto->dst_mask bits. */ + case R_LARCH_ADD6: + case R_LARCH_SUB6: + { + bfd_vma word = bfd_get (howto->bitsize, input_bfd, + contents + rel->r_offset); + word = (word & ~howto->dst_mask) | (value & howto->dst_mask); + bfd_put (howto->bitsize, input_bfd, word, contents + rel->r_offset); + r = bfd_reloc_ok; + break; + } + + /* Not need to read the original value, just write the new value. */ case R_LARCH_ADD8: case R_LARCH_ADD16: case R_LARCH_ADD24: case R_LARCH_ADD32: case R_LARCH_ADD64: - r = loongarch_check_offset (rel, input_section); - if (r != bfd_reloc_ok) - break; - - opr1 = bfd_get (bits, input_bfd, contents + rel->r_offset); - bfd_put (bits, input_bfd, opr1 + value, contents + rel->r_offset); - break; - case R_LARCH_SUB8: case R_LARCH_SUB16: case R_LARCH_SUB24: case R_LARCH_SUB32: case R_LARCH_SUB64: - r = loongarch_check_offset (rel, input_section); - if (r != bfd_reloc_ok) + { + /* Because add/sub reloc is processed separately, + so the high bits is invalid. */ + bfd_vma word = value & howto->dst_mask; + bfd_put (howto->bitsize, input_bfd, word, contents + rel->r_offset); + r = bfd_reloc_ok; break; + } - opr1 = bfd_get (bits, input_bfd, contents + rel->r_offset); - bfd_put (bits, input_bfd, opr1 - value, contents + rel->r_offset); - break; + case R_LARCH_ADD_ULEB128: + case R_LARCH_SUB_ULEB128: + { + unsigned int len = 0; + /* Before write uleb128, first read it to get it's length. */ + _bfd_read_unsigned_leb128 (input_bfd, contents + rel->r_offset, &len); + loongarch_write_unsigned_leb128 (contents + rel->r_offset, len, value); + r = bfd_reloc_ok; + break; + } /* For eh_frame and debug info. */ case R_LARCH_32_PCREL: - value -= sec_addr (input_section) + rel->r_offset; - value += rel->r_addend; - bfd_vma word = bfd_get (howto->bitsize, input_bfd, - contents + rel->r_offset); - word = (word & ~howto->dst_mask) | (value & howto->dst_mask); - bfd_put (howto->bitsize, input_bfd, word, contents + rel->r_offset); - r = bfd_reloc_ok; - break; + case R_LARCH_64_PCREL: + { + value -= sec_addr (input_section) + rel->r_offset; + value += rel->r_addend; + bfd_vma word = bfd_get (howto->bitsize, input_bfd, + contents + rel->r_offset); + word = (word & ~howto->dst_mask) | (value & howto->dst_mask); + bfd_put (howto->bitsize, input_bfd, word, contents + rel->r_offset); + r = bfd_reloc_ok; + break; + } /* New reloc type. R_LARCH_B16 ~ R_LARCH_TLS_GD_HI20. */ @@ -2082,6 +2121,7 @@ perform_relocation (const Elf_Internal_Rela *rel, asection *input_section, case R_LARCH_TLS_LD_HI20: case R_LARCH_TLS_GD_PC_HI20: case R_LARCH_TLS_GD_HI20: + case R_LARCH_PCREL20_S2: r = loongarch_check_offset (rel, input_section); if (r != bfd_reloc_ok) break; @@ -2246,26 +2286,65 @@ loongarch_reloc_is_fatal (struct bfd_link_info *info, return fatal; } +/* If lo12 immediate > 0x7ff, because sign-extend caused by addi.d/ld.d, + hi20 immediate need to add 0x1. + For example: pc 0x120000000, symbol 0x120000812 + lo12 immediate is 0x812, 0x120000812 & 0xfff = 0x812 + hi20 immediate is 1, because lo12 imm > 0x7ff, symbol need to add 0x1000 + (((0x120000812 + 0x1000) & ~0xfff) - (0x120000000 & ~0xfff)) >> 12 = 0x1 + + At run: + pcalau12i $t0, hi20 (0x1) + $t0 = 0x120000000 + (0x1 << 12) = 0x120001000 + addi.d $t0, $t0, lo12 (0x812) + $t0 = 0x120001000 + 0xfffffffffffff812 (-(0x1000 - 0x812) = -0x7ee) + = 0x120001000 - 0x7ee (0x1000 - 0x7ee = 0x812) + = 0x120000812 + Without hi20 add 0x1000, the result 0x120000000 - 0x7ee = 0x11ffff812 is + error. + 0x1000 + sign-extend-to64(0x8xx) = 0x8xx. */ #define RELOCATE_CALC_PC32_HI20(relocation, pc) \ ({ \ - bfd_vma lo = (relocation) & ((bfd_vma)0xfff); \ - pc = pc & (~(bfd_vma)0xfff); \ - if (lo > 0x7ff) \ - { \ + bfd_vma __lo = (relocation) & ((bfd_vma)0xfff); \ + relocation = (relocation & ~(bfd_vma)0xfff) \ + - (pc & ~(bfd_vma)0xfff); \ + if (__lo > 0x7ff) \ relocation += 0x1000; \ - } \ - relocation &= ~(bfd_vma)0xfff; \ - relocation -= pc; \ }) +/* For example: pc is 0x11000010000100, symbol is 0x1812348ffff812 + offset = (0x1812348ffff812 & ~0xfff) - (0x11000010000100 & ~0xfff) + = 0x712347ffff000 + lo12: 0x1812348ffff812 & 0xfff = 0x812 + hi20: 0x7ffff + 0x1(lo12 > 0x7ff) = 0x80000 + lo20: 0x71234 - 0x1(lo12 > 0x7ff) + 0x1(hi20 > 0x7ffff) + hi12: 0x0 + + pcalau12i $t1, hi20 (0x80000) + $t1 = 0x11000010000100 + sign-extend(0x80000 << 12) + = 0x11000010000100 + 0xffffffff80000000 + = 0x10ffff90000000 + addi.d $t0, $zero, lo12 (0x812) + $t0 = 0xfffffffffffff812 (if lo12 > 0x7ff, because sign-extend, + lo20 need to sub 0x1) + lu32i.d $t0, lo12 (0x71234) + $t0 = {0x71234, 0xfffff812} + = 0x71234fffff812 + lu52i.d $t0, hi12 (0x0) + $t0 = {0x0, 0x71234fffff812} + = 0x71234fffff812 + add.d $t1, $t1, $t0 + $t1 = 0x10ffff90000000 + 0x71234fffff812 + = 0x1812348ffff812. */ #define RELOCATE_CALC_PC64_HI32(relocation, pc) \ ({ \ - bfd_vma lo = (relocation) & ((bfd_vma)0xfff); \ - if (lo > 0x7ff) \ - { \ - relocation -= 0x100000000; \ - } \ - relocation -= (pc & ~(bfd_vma)0xffffffff); \ + bfd_vma __lo = (relocation & (bfd_vma)0xfff); \ + relocation = (relocation & ~(bfd_vma)0xfff) \ + - (pc & ~(bfd_vma)0xfff); \ + if (__lo > 0x7ff) \ + relocation += (0x1000 - 0x100000000); \ + if (relocation & 0x80000000) \ + relocation += 0x100000000; \ }) static int @@ -2527,29 +2606,49 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, relocation += rel->r_addend; break; + case R_LARCH_ADD6: case R_LARCH_ADD8: case R_LARCH_ADD16: case R_LARCH_ADD24: case R_LARCH_ADD32: case R_LARCH_ADD64: + { + bfd_vma old_value = bfd_get (howto->bitsize, input_bfd, + contents + rel->r_offset); + relocation = old_value + relocation + rel->r_addend; + break; + } + + case R_LARCH_SUB6: case R_LARCH_SUB8: case R_LARCH_SUB16: case R_LARCH_SUB24: case R_LARCH_SUB32: case R_LARCH_SUB64: - if (resolved_dynly) - fatal = (loongarch_reloc_is_fatal - (info, input_bfd, input_section, rel, howto, - bfd_reloc_undefined, is_undefweak, name, - "Can't be resolved dynamically. " - "If this procedure is hand-written assembly,\n" - "there must be something like '.dword sym1 - sym2' " - "to generate these relocs\n" - "and we can't get known link-time address of " - "these symbols.")); - else - relocation += rel->r_addend; - break; + { + bfd_vma old_value = bfd_get (howto->bitsize, input_bfd, + contents + rel->r_offset); + relocation = old_value - relocation - rel->r_addend; + break; + } + + case R_LARCH_ADD_ULEB128: + case R_LARCH_SUB_ULEB128: + { + /* Get the value and length of the uleb128 data. */ + unsigned int len = 0; + bfd_vma old_value = _bfd_read_unsigned_leb128 (input_bfd, + contents + rel->r_offset, &len); + + if (R_LARCH_ADD_ULEB128 == ELFNN_R_TYPE (rel->r_info)) + relocation = old_value + relocation + rel->r_addend; + else if (R_LARCH_SUB_ULEB128 == ELFNN_R_TYPE (rel->r_info)) + relocation = old_value - relocation - rel->r_addend; + + bfd_vma mask = (1 << (7 * len)) - 1; + relocation &= mask; + break; + } case R_LARCH_TLS_DTPREL32: case R_LARCH_TLS_DTPREL64: @@ -3089,6 +3188,15 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, break; + case R_LARCH_PCREL20_S2: + unresolved_reloc = false; + if (h && h->plt.offset != MINUS_ONE) + relocation = sec_addr (plt) + h->plt.offset; + else + relocation += rel->r_addend; + relocation -= pc; + break; + case R_LARCH_PCALA_HI20: unresolved_reloc = false; if (h && h->plt.offset != MINUS_ONE) @@ -3115,15 +3223,15 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, relocation += rel->r_addend; { - relocation &= 0xfff; - /* Signed extend. */ - relocation = (relocation ^ 0x800) - 0x800; - /* For 2G jump, generate pcalau12i, jirl. */ /* If use jirl, turns to R_LARCH_B16. */ uint32_t insn = bfd_get (32, input_bfd, contents + rel->r_offset); if ((insn & 0x4c000000) == 0x4c000000) { + relocation &= 0xfff; + /* Signed extend. */ + relocation = (relocation ^ 0x800) - 0x800; + rel->r_info = ELFNN_R_INFO (r_symndx, R_LARCH_B16); howto = loongarch_elf_rtype_to_howto (input_bfd, R_LARCH_B16); } @@ -3262,13 +3370,12 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, + (idx * GOT_ENTRY_SIZE) - sec_addr (htab->elf.sgot); } + relocation = got_off + sec_addr (got); } - if (r_type == R_LARCH_GOT_PC_LO12) - relocation &= (bfd_vma)0xfff; - else if (r_type == R_LARCH_GOT64_PC_LO20 - || r_type == R_LARCH_GOT64_PC_HI12) + if (r_type == R_LARCH_GOT64_PC_HI12 + || r_type == R_LARCH_GOT64_PC_LO20) RELOCATE_CALC_PC64_HI32 (relocation, pc); break; @@ -3426,15 +3533,16 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, if ((tls_type & GOT_TLS_GD) && (tls_type & GOT_TLS_IE)) relocation += 2 * GOT_ENTRY_SIZE; - if (r_type == R_LARCH_TLS_IE_PC_LO12) - relocation &= (bfd_vma)0xfff; - else if (r_type == R_LARCH_TLS_IE64_PC_LO20 - || r_type == R_LARCH_TLS_IE64_PC_HI12) + if (r_type == R_LARCH_TLS_IE64_PC_LO20 + || r_type == R_LARCH_TLS_IE64_PC_HI12) RELOCATE_CALC_PC64_HI32 (relocation, pc); break; case R_LARCH_RELAX: + case R_LARCH_ALIGN: + r = bfd_reloc_continue; + unresolved_reloc = false; break; default: @@ -3525,6 +3633,409 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, return !fatal; } +static bool +loongarch_relax_delete_bytes (bfd *abfd, + asection *sec, + bfd_vma addr, + size_t count, + struct bfd_link_info *link_info) +{ + unsigned int i, symcount; + bfd_vma toaddr = sec->size; + struct elf_link_hash_entry **sym_hashes = elf_sym_hashes (abfd); + Elf_Internal_Shdr *symtab_hdr = &elf_tdata (abfd)->symtab_hdr; + unsigned int sec_shndx = _bfd_elf_section_from_bfd_section (abfd, sec); + struct bfd_elf_section_data *data = elf_section_data (sec); + bfd_byte *contents = data->this_hdr.contents; + + /* Actually delete the bytes. */ + sec->size -= count; + memmove (contents + addr, contents + addr + count, toaddr - addr - count); + + /* Adjust the location of all of the relocs. Note that we need not + adjust the addends, since all PC-relative references must be against + symbols, which we will adjust below. */ + for (i = 0; i < sec->reloc_count; i++) + if (data->relocs[i].r_offset > addr && data->relocs[i].r_offset < toaddr) + data->relocs[i].r_offset -= count; + + /* Adjust the local symbols defined in this section. */ + for (i = 0; i < symtab_hdr->sh_info; i++) + { + Elf_Internal_Sym *sym = (Elf_Internal_Sym *) symtab_hdr->contents + i; + if (sym->st_shndx == sec_shndx) + { + /* If the symbol is in the range of memory we just moved, we + have to adjust its value. */ + if (sym->st_value > addr && sym->st_value <= toaddr) + sym->st_value -= count; + + /* If the symbol *spans* the bytes we just deleted (i.e. its + *end* is in the moved bytes but its *start* isn't), then we + must adjust its size. + + This test needs to use the original value of st_value, otherwise + we might accidentally decrease size when deleting bytes right + before the symbol. But since deleted relocs can't span across + symbols, we can't have both a st_value and a st_size decrease, + so it is simpler to just use an else. */ + else if (sym->st_value <= addr + && sym->st_value + sym->st_size > addr + && sym->st_value + sym->st_size <= toaddr) + sym->st_size -= count; + } + } + + /* Now adjust the global symbols defined in this section. */ + symcount = ((symtab_hdr->sh_size / sizeof (ElfNN_External_Sym)) + - symtab_hdr->sh_info); + + for (i = 0; i < symcount; i++) + { + struct elf_link_hash_entry *sym_hash = sym_hashes[i]; + + /* The '--wrap SYMBOL' option is causing a pain when the object file, + containing the definition of __wrap_SYMBOL, includes a direct + call to SYMBOL as well. Since both __wrap_SYMBOL and SYMBOL reference + the same symbol (which is __wrap_SYMBOL), but still exist as two + different symbols in 'sym_hashes', we don't want to adjust + the global symbol __wrap_SYMBOL twice. + + The same problem occurs with symbols that are versioned_hidden, as + foo becomes an alias for foo@BAR, and hence they need the same + treatment. */ + if (link_info->wrap_hash != NULL + || sym_hash->versioned != unversioned) + { + struct elf_link_hash_entry **cur_sym_hashes; + + /* Loop only over the symbols which have already been checked. */ + for (cur_sym_hashes = sym_hashes; cur_sym_hashes < &sym_hashes[i]; + cur_sym_hashes++) + { + /* If the current symbol is identical to 'sym_hash', that means + the symbol was already adjusted (or at least checked). */ + if (*cur_sym_hashes == sym_hash) + break; + } + /* Don't adjust the symbol again. */ + if (cur_sym_hashes < &sym_hashes[i]) + continue; + } + + if ((sym_hash->root.type == bfd_link_hash_defined + || sym_hash->root.type == bfd_link_hash_defweak) + && sym_hash->root.u.def.section == sec) + { + /* As above, adjust the value if needed. */ + if (sym_hash->root.u.def.value > addr + && sym_hash->root.u.def.value <= toaddr) + sym_hash->root.u.def.value -= count; + + /* As above, adjust the size if needed. */ + else if (sym_hash->root.u.def.value <= addr + && sym_hash->root.u.def.value + sym_hash->size > addr + && sym_hash->root.u.def.value + sym_hash->size <= toaddr) + sym_hash->size -= count; + } + } + + return true; +} + +/* Relax pcalau12i,addi.d => pcaddi. */ +static bool +loongarch_relax_pcala_addi (bfd *abfd, asection *sec, + Elf_Internal_Rela *rel_hi, bfd_vma symval) +{ + bfd_byte *contents = elf_section_data (sec)->this_hdr.contents; + Elf_Internal_Rela *rel_lo = rel_hi + 2; + uint32_t pca = bfd_get (32, abfd, contents + rel_hi->r_offset); + uint32_t add = bfd_get (32, abfd, contents + rel_lo->r_offset); + uint32_t rd = pca & 0x1f; + bfd_vma pc = sec_addr (sec) + rel_hi->r_offset; + const uint32_t addi_d = 0x02c00000; + const uint32_t pcaddi = 0x18000000; + + /* Is pcalau12i + addi.d insns? */ + if ((ELFNN_R_TYPE (rel_lo->r_info) != R_LARCH_PCALA_LO12) + || (ELFNN_R_TYPE ((rel_lo + 1)->r_info) != R_LARCH_RELAX) + || (ELFNN_R_TYPE ((rel_hi + 1)->r_info) != R_LARCH_RELAX) + || (rel_hi->r_offset + 4 != rel_lo->r_offset) + || ((add & addi_d) != addi_d) + /* Is pcalau12i $rd + addi.d $rd,$rd? */ + || ((add & 0x1f) != rd) + || (((add >> 5) & 0x1f) != rd) + /* Can be relaxed to pcaddi? */ + || (symval & 0x3) /* 4 bytes align. */ + || ((bfd_signed_vma)(symval - pc) < (bfd_signed_vma)(int32_t)0xffe00000) + || ((bfd_signed_vma)(symval - pc) > (bfd_signed_vma)(int32_t)0x1ffffc)) + return false; + + pca = pcaddi | rd; + bfd_put (32, abfd, pca, contents + rel_hi->r_offset); + + /* Adjust relocations. */ + rel_hi->r_info = ELFNN_R_INFO (ELFNN_R_SYM (rel_hi->r_info), + R_LARCH_PCREL20_S2); + rel_lo->r_info = ELFNN_R_INFO (ELFNN_R_SYM (rel_hi->r_info), + R_LARCH_DELETE); + + return true; +} + +/* Relax pcalau12i,ld.d => pcalau12i,addi.d. */ +static bool +loongarch_relax_pcala_ld (bfd *abfd, asection *sec, + Elf_Internal_Rela *rel_hi) +{ + bfd_byte *contents = elf_section_data (sec)->this_hdr.contents; + Elf_Internal_Rela *rel_lo = rel_hi + 2; + uint32_t pca = bfd_get (32, abfd, contents + rel_hi->r_offset); + uint32_t ld = bfd_get (32, abfd, contents + rel_lo->r_offset); + uint32_t rd = pca & 0x1f; + const uint32_t ld_d = 0x28c00000; + uint32_t addi_d = 0x02c00000; + + if ((ELFNN_R_TYPE (rel_lo->r_info) != R_LARCH_GOT_PC_LO12) + || (ELFNN_R_TYPE ((rel_lo + 1)->r_info) != R_LARCH_RELAX) + || (ELFNN_R_TYPE ((rel_hi + 1)->r_info) != R_LARCH_RELAX) + || (rel_hi->r_offset + 4 != rel_lo->r_offset) + || ((ld & 0x1f) != rd) + || (((ld >> 5) & 0x1f) != rd) + || ((ld & ld_d) != ld_d)) + return false; + + addi_d = addi_d | (rd << 5) | rd; + bfd_put (32, abfd, addi_d, contents + rel_lo->r_offset); + + rel_hi->r_info = ELFNN_R_INFO (ELFNN_R_SYM (rel_hi->r_info), + R_LARCH_PCALA_HI20); + rel_lo->r_info = ELFNN_R_INFO (ELFNN_R_SYM (rel_lo->r_info), + R_LARCH_PCALA_LO12); + return true; +} + +/* Called by after_allocation to set the information of data segment + before relaxing. */ + +void +bfd_elfNN_loongarch_set_data_segment_info (struct bfd_link_info *info, + int *data_segment_phase) +{ + struct loongarch_elf_link_hash_table *htab = loongarch_elf_hash_table (info); + htab->data_segment_phase = data_segment_phase; +} + +/* Implement R_LARCH_ALIGN by deleting excess alignment NOPs. + Once we've handled an R_LARCH_ALIGN, we can't relax anything else. */ +static bool +loongarch_relax_align (bfd *abfd, asection *sec, + asection *sym_sec, + struct bfd_link_info *link_info, + Elf_Internal_Rela *rel, + bfd_vma symval) +{ + bfd_byte *contents = elf_section_data (sec)->this_hdr.contents; + bfd_vma alignment = 1, pos; + while (alignment <= rel->r_addend) + alignment *= 2; + + symval -= rel->r_addend; + bfd_vma aligned_addr = ((symval - 1) & ~(alignment - 1)) + alignment; + bfd_vma nop_bytes = aligned_addr - symval; + + /* Once we've handled an R_LARCH_ALIGN, we can't relax anything else. */ + sec->sec_flg0 = true; + + /* Make sure there are enough NOPs to actually achieve the alignment. */ + if (rel->r_addend < nop_bytes) + { + _bfd_error_handler + (_("%pB(%pA+%#" PRIx64 "): %" PRId64 " bytes required for alignment " + "to %" PRId64 "-byte boundary, but only %" PRId64 " present"), + abfd, sym_sec, (uint64_t) rel->r_offset, + (int64_t) nop_bytes, (int64_t) alignment, (int64_t) rel->r_addend); + bfd_set_error (bfd_error_bad_value); + return false; + } + + /* Delete the reloc. */ + rel->r_info = ELFNN_R_INFO (0, R_LARCH_NONE); + + /* If the number of NOPs is already correct, there's nothing to do. */ + if (nop_bytes == rel->r_addend) + return true; + + /* Write as many LOONGARCH NOPs as we need. */ + for (pos = 0; pos < (nop_bytes & -4); pos += 4) + bfd_putl32 (LARCH_NOP, contents + rel->r_offset + pos); + + /* Delete the excess NOPs. */ + return loongarch_relax_delete_bytes (abfd, sec, rel->r_offset + nop_bytes, + rel->r_addend - nop_bytes, link_info); +} + +static bool +loongarch_elf_relax_section (bfd *abfd, asection *sec, + struct bfd_link_info *info, + bool *again) +{ + struct loongarch_elf_link_hash_table *htab = loongarch_elf_hash_table (info); + Elf_Internal_Shdr *symtab_hdr = &elf_symtab_hdr (abfd); + struct bfd_elf_section_data *data = elf_section_data (sec); + Elf_Internal_Rela *relocs; + *again = false; + + if (bfd_link_relocatable (info) + || sec->sec_flg0 + || (sec->flags & SEC_RELOC) == 0 + || sec->reloc_count == 0 + || elf_seg_map (info->output_bfd) == NULL + || (info->disable_target_specific_optimizations + && info->relax_pass == 0) + /* The exp_seg_relro_adjust is enum phase_enum (0x4), + and defined in ld/ldexp.h. */ + || *(htab->data_segment_phase) == 4) + return true; + + if (data->relocs) + relocs = data->relocs; + else if (!(relocs = _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, + info->keep_memory))) + return true; + + if (!data->this_hdr.contents + && !bfd_malloc_and_get_section (abfd, sec, &data->this_hdr.contents)) + return true; + + if (symtab_hdr->sh_info != 0 + && !symtab_hdr->contents + && !(symtab_hdr->contents = + (unsigned char *) bfd_elf_get_elf_syms (abfd, symtab_hdr, + symtab_hdr->sh_info, + 0, NULL, NULL, NULL))) + return true; + + data->relocs = relocs; + + for (unsigned int i = 0; i < sec->reloc_count; i++) + { + Elf_Internal_Rela *rel = relocs + i; + asection *sym_sec; + bfd_vma symval; + unsigned long r_symndx = ELFNN_R_SYM (rel->r_info); + bool local_got = false; + char symtype; + struct elf_link_hash_entry *h = NULL; + + if (r_symndx < symtab_hdr->sh_info) + { + Elf_Internal_Sym *sym = (Elf_Internal_Sym *)symtab_hdr->contents + + r_symndx; + if (ELF_ST_TYPE (sym->st_info) == STT_GNU_IFUNC) + continue; + + if (sym->st_shndx == SHN_UNDEF) + { + sym_sec = sec; + symval = rel->r_offset; + } + else + { + sym_sec = elf_elfsections (abfd)[sym->st_shndx]->bfd_section; + symval = sym->st_value; + } + symtype = ELF_ST_TYPE (sym->st_info); + } + else + { + r_symndx = ELFNN_R_SYM (rel->r_info) - symtab_hdr->sh_info; + h = elf_sym_hashes (abfd)[r_symndx]; + + while (h->root.type == bfd_link_hash_indirect + || h->root.type == bfd_link_hash_warning) + h = (struct elf_link_hash_entry *) h->root.u.i.link; + + /* Disable the relaxation for ifunc. */ + if (h != NULL && h->type == STT_GNU_IFUNC) + continue; + + if ((h->root.type == bfd_link_hash_defined + || h->root.type == bfd_link_hash_defweak) + && h->root.u.def.section != NULL + && h->root.u.def.section->output_section != NULL) + { + symval = h->root.u.def.value; + sym_sec = h->root.u.def.section; + } + else + continue; + + if (h && bfd_link_executable (info) + && SYMBOL_REFERENCES_LOCAL (info, h)) + local_got = true; + symtype = h->type; + } + + if (sym_sec->sec_info_type == SEC_INFO_TYPE_MERGE + && (sym_sec->flags & SEC_MERGE)) + { + if (symtype == STT_SECTION) + symval += rel->r_addend; + + symval = _bfd_merged_section_offset (abfd, &sym_sec, + elf_section_data (sym_sec)->sec_info, + symval); + + if (symtype != STT_SECTION) + symval += rel->r_addend; + } + else + symval += rel->r_addend; + + symval += sec_addr (sym_sec); + + switch (ELFNN_R_TYPE (rel->r_info)) + { + case R_LARCH_ALIGN: + if (2 == info->relax_pass) + loongarch_relax_align (abfd, sec, sym_sec, info, rel, symval); + break; + case R_LARCH_DELETE: + if (info->relax_pass == 1) + { + loongarch_relax_delete_bytes (abfd, sec, rel->r_offset, 4, info); + rel->r_info = ELFNN_R_INFO (0, R_LARCH_NONE); + } + break; + case R_LARCH_PCALA_HI20: + if (info->relax_pass == 0) + { + if (i + 4 > sec->reloc_count) + break; + loongarch_relax_pcala_addi (abfd, sec, rel, symval); + } + break; + case R_LARCH_GOT_PC_HI20: + if (local_got) + { + if (i + 4 > sec->reloc_count) + break; + if (loongarch_relax_pcala_ld (abfd, sec, rel)) + { + loongarch_relax_pcala_addi (abfd, sec, rel, symval); + } + } + break; + default: + break; + } + } + + return true; +} + /* Finish up dynamic symbol handling. We set the contents of various dynamic sections here. */ @@ -3536,12 +4047,6 @@ loongarch_elf_finish_dynamic_symbol (bfd *output_bfd, { struct loongarch_elf_link_hash_table *htab = loongarch_elf_hash_table (info); const struct elf_backend_data *bed = get_elf_backend_data (output_bfd); - asection *rela_dyn = bfd_get_section_by_name (output_bfd, ".rela.dyn"); - struct bfd_link_order *lo = NULL; - Elf_Internal_Rela *slot = NULL, *last_slot = NULL; - - if (rela_dyn) - lo = rela_dyn->map_head.link_order; if (h->plt.offset != MINUS_ONE) { @@ -3551,7 +4056,6 @@ loongarch_elf_finish_dynamic_symbol (bfd *output_bfd, uint32_t plt_entry[PLT_ENTRY_INSNS]; bfd_byte *loc; Elf_Internal_Rela rela; - asection *rela_sec = NULL; if (htab->elf.splt) { @@ -3609,26 +4113,7 @@ loongarch_elf_finish_dynamic_symbol (bfd *output_bfd, + h->root.u.def.section->output_section->vma + h->root.u.def.section->output_offset); - /* Find the space after dyn sort. */ - while (slot == last_slot || slot->r_offset != 0) - { - if (slot != last_slot) - { - slot++; - continue; - } - - BFD_ASSERT (lo != NULL); - rela_sec = lo->u.indirect.section; - lo = lo->next; - - slot = (Elf_Internal_Rela *)rela_sec->contents; - last_slot = (Elf_Internal_Rela *)(rela_sec->contents + - rela_sec->size); - } - - bed->s->swap_reloca_out (output_bfd, &rela, (bfd_byte *)slot); - rela_sec->reloc_count++; + loongarch_elf_append_rela (output_bfd, relplt, &rela); } else { @@ -3795,7 +4280,7 @@ loongarch_finish_dyn (bfd *output_bfd, struct bfd_link_info *info, bfd *dynobj, /* Finish up local dynamic symbol handling. We set the contents of various dynamic sections here. */ -static bool +static int elfNN_loongarch_finish_local_dynamic_symbol (void **slot, void *inf) { struct elf_link_hash_entry *h = (struct elf_link_hash_entry *) *slot; @@ -3804,6 +4289,33 @@ elfNN_loongarch_finish_local_dynamic_symbol (void **slot, void *inf) return loongarch_elf_finish_dynamic_symbol (info->output_bfd, info, h, NULL); } +/* Value of struct elf_backend_data->elf_backend_output_arch_local_syms, + this function is called before elf_link_sort_relocs. + So relocation R_LARCH_IRELATIVE for local ifunc can be append to + .rela.dyn (.rela.got) by loongarch_elf_append_rela. */ + +static bool +elf_loongarch_output_arch_local_syms + (bfd *output_bfd ATTRIBUTE_UNUSED, + struct bfd_link_info *info, + void *flaginfo ATTRIBUTE_UNUSED, + int (*func) (void *, const char *, + Elf_Internal_Sym *, + asection *, + struct elf_link_hash_entry *) ATTRIBUTE_UNUSED) +{ + struct loongarch_elf_link_hash_table *htab = loongarch_elf_hash_table (info); + if (htab == NULL) + return false; + + /* Fill PLT and GOT entries for local STT_GNU_IFUNC symbols. */ + htab_traverse (htab->loc_hash_table, + elfNN_loongarch_finish_local_dynamic_symbol, + info); + + return true; +} + static bool loongarch_elf_finish_dynamic_sections (bfd *output_bfd, struct bfd_link_info *info) @@ -3882,10 +4394,6 @@ loongarch_elf_finish_dynamic_sections (bfd *output_bfd, elf_section_data (output_section)->this_hdr.sh_entsize = GOT_ENTRY_SIZE; } - /* Fill PLT and GOT entries for local STT_GNU_IFUNC symbols. */ - htab_traverse (htab->loc_hash_table, - (void *) elfNN_loongarch_finish_local_dynamic_symbol, info); - return true; } @@ -4150,6 +4658,8 @@ elf_loongarch64_hash_symbol (struct elf_link_hash_entry *h) #define elf_backend_size_dynamic_sections loongarch_elf_size_dynamic_sections #define elf_backend_relocate_section loongarch_elf_relocate_section #define elf_backend_finish_dynamic_symbol loongarch_elf_finish_dynamic_symbol +#define elf_backend_output_arch_local_syms \ + elf_loongarch_output_arch_local_syms #define elf_backend_finish_dynamic_sections \ loongarch_elf_finish_dynamic_sections #define elf_backend_object_p loongarch_elf_object_p @@ -4158,5 +4668,6 @@ elf_loongarch64_hash_symbol (struct elf_link_hash_entry *h) #define elf_backend_grok_prstatus loongarch_elf_grok_prstatus #define elf_backend_grok_psinfo loongarch_elf_grok_psinfo #define elf_backend_hash_symbol elf_loongarch64_hash_symbol +#define bfd_elfNN_bfd_relax_section loongarch_elf_relax_section #include "elfNN-target.h" diff --git a/bfd/elfxx-loongarch.c b/bfd/elfxx-loongarch.c index 1455b57a..23c5e477 100644 --- a/bfd/elfxx-loongarch.c +++ b/bfd/elfxx-loongarch.c @@ -34,7 +34,7 @@ typedef struct loongarch_reloc_howto_type_struct /* The first must be reloc_howto_type! */ reloc_howto_type howto; bfd_reloc_code_real_type bfd_type; - bool (*adjust_reloc_bits)(reloc_howto_type *, bfd_vma *); + bool (*adjust_reloc_bits)(bfd *, reloc_howto_type *, bfd_vma *); const char *larch_reloc_type_name; } loongarch_reloc_howto_type; @@ -52,13 +52,17 @@ typedef struct loongarch_reloc_howto_type_struct { EMPTY_HOWTO (C), BFD_RELOC_NONE, NULL, NULL } static bool -reloc_bits (reloc_howto_type *howto, bfd_vma *val); +reloc_bits (bfd *abfd, reloc_howto_type *howto, bfd_vma *val); static bool -reloc_bits_b16 (reloc_howto_type *howto, bfd_vma *fix_val); -static bool -reloc_bits_b21 (reloc_howto_type *howto, bfd_vma *fix_val); -static bool -reloc_bits_b26 (reloc_howto_type *howto, bfd_vma *val); +reloc_sign_bits (bfd *abfd, reloc_howto_type *howto, bfd_vma *fix_val); + +static bfd_reloc_status_type +loongarch_elf_add_sub_reloc (bfd *, arelent *, asymbol *, void *, + asection *, bfd *, char **); + +static bfd_reloc_status_type +loongarch_elf_add_sub_reloc_uleb128 (bfd *, arelent *, asymbol *, void *, + asection *, bfd *, char **); /* This does not include any relocation information, but should be good enough for GDB or objdump to read the file. */ @@ -447,7 +451,7 @@ static loongarch_reloc_howto_type loongarch_howto_table[] = 0x3fffc00, /* dst_mask */ false, /* pcrel_offset */ BFD_RELOC_LARCH_SOP_POP_32_S_10_16_S2, /* bfd_reloc_code_real_type */ - reloc_bits_b16, /* adjust_reloc_bits */ + reloc_sign_bits, /* adjust_reloc_bits */ NULL), /* larch_reloc_type_name */ LOONGARCH_HOWTO (R_LARCH_SOP_POP_32_S_5_20, /* type (43). */ @@ -483,7 +487,7 @@ static loongarch_reloc_howto_type loongarch_howto_table[] = false, /* pcrel_offset */ BFD_RELOC_LARCH_SOP_POP_32_S_0_5_10_16_S2, /* bfd_reloc_code_real_type */ - reloc_bits_b21, /* adjust_reloc_bits */ + reloc_sign_bits, /* adjust_reloc_bits */ NULL), /* larch_reloc_type_name */ LOONGARCH_HOWTO (R_LARCH_SOP_POP_32_S_0_10_10_16_S2, /* type (45). */ @@ -501,7 +505,7 @@ static loongarch_reloc_howto_type loongarch_howto_table[] = false, /* pcrel_offset */ BFD_RELOC_LARCH_SOP_POP_32_S_0_10_10_16_S2, /* bfd_reloc_code_real_type */ - reloc_bits_b26, /* adjust_reloc_bits */ + reloc_sign_bits, /* adjust_reloc_bits */ NULL), /* larch_reloc_type_name */ LOONGARCH_HOWTO (R_LARCH_SOP_POP_32_U, /* type (46). */ @@ -521,175 +525,185 @@ static loongarch_reloc_howto_type loongarch_howto_table[] = reloc_bits, /* adjust_reloc_bits */ NULL), /* larch_reloc_type_name */ + /* 8-bit in-place addition, for local label subtraction. */ LOONGARCH_HOWTO (R_LARCH_ADD8, /* type (47). */ 0, /* rightshift. */ - 2, /* size. */ + 1, /* size. */ 8, /* bitsize. */ false, /* pc_relative. */ 0, /* bitpos. */ - complain_overflow_signed, /* complain_on_overflow. */ - bfd_elf_generic_reloc, /* special_function. */ + complain_overflow_dont, /* complain_on_overflow. */ + loongarch_elf_add_sub_reloc, /* special_function. */ "R_LARCH_ADD8", /* name. */ false, /* partial_inplace. */ - 0, /* src_mask */ - ALL_ONES, /* dst_mask */ - false, /* pcrel_offset */ - BFD_RELOC_LARCH_ADD8, /* bfd_reloc_code_real_type */ - NULL, /* adjust_reloc_bits */ - NULL), /* larch_reloc_type_name */ - + 0, /* src_mask. */ + 0xff, /* dst_mask. */ + false, /* pcrel_offset. */ + BFD_RELOC_LARCH_ADD8, /* bfd_reloc_code_real_type. */ + NULL, /* adjust_reloc_bits. */ + NULL), /* larch_reloc_type_name. */ + + /* 16-bit in-place addition, for local label subtraction. */ LOONGARCH_HOWTO (R_LARCH_ADD16, /* type (48). */ 0, /* rightshift. */ 2, /* size. */ 16, /* bitsize. */ false, /* pc_relative. */ 0, /* bitpos. */ - complain_overflow_signed, /* complain_on_overflow. */ - bfd_elf_generic_reloc, /* special_function. */ + complain_overflow_dont, /* complain_on_overflow. */ + loongarch_elf_add_sub_reloc, /* special_function. */ "R_LARCH_ADD16", /* name. */ false, /* partial_inplace. */ - 0, /* src_mask */ - ALL_ONES, /* dst_mask */ - false, /* pcrel_offset */ - BFD_RELOC_LARCH_ADD16, /* bfd_reloc_code_real_type */ - NULL, /* adjust_reloc_bits */ - NULL), /* larch_reloc_type_name */ - + 0, /* src_mask. */ + 0xffff, /* dst_mask. */ + false, /* pcrel_offset. */ + BFD_RELOC_LARCH_ADD16, /* bfd_reloc_code_real_type. */ + NULL, /* adjust_reloc_bits. */ + NULL), /* larch_reloc_type_name. */ + + /* 24-bit in-place addition, for local label subtraction. */ LOONGARCH_HOWTO (R_LARCH_ADD24, /* type (49). */ 0, /* rightshift. */ - 2, /* size. */ + 3, /* size. */ 24, /* bitsize. */ false, /* pc_relative. */ 0, /* bitpos. */ - complain_overflow_signed, /* complain_on_overflow. */ - bfd_elf_generic_reloc, /* special_function. */ + complain_overflow_dont, /* complain_on_overflow. */ + loongarch_elf_add_sub_reloc, /* special_function. */ "R_LARCH_ADD24", /* name. */ false, /* partial_inplace. */ - 0, /* src_mask */ - ALL_ONES, /* dst_mask */ - false, /* pcrel_offset */ - BFD_RELOC_LARCH_ADD24, /* bfd_reloc_code_real_type */ - NULL, /* adjust_reloc_bits */ - NULL), /* larch_reloc_type_name */ - + 0, /* src_mask. */ + 0xffffff, /* dst_mask. */ + false, /* pcrel_offset. */ + BFD_RELOC_LARCH_ADD24, /* bfd_reloc_code_real_type. */ + NULL, /* adjust_reloc_bits. */ + NULL), /* larch_reloc_type_name. */ + + /* 32-bit in-place addition, for local label subtraction. */ LOONGARCH_HOWTO (R_LARCH_ADD32, /* type (50). */ 0, /* rightshift. */ - 2, /* size. */ + 4, /* size. */ 32, /* bitsize. */ false, /* pc_relative. */ 0, /* bitpos. */ - complain_overflow_signed, /* complain_on_overflow. */ - bfd_elf_generic_reloc, /* special_function. */ + complain_overflow_dont, /* complain_on_overflow. */ + loongarch_elf_add_sub_reloc, /* special_function. */ "R_LARCH_ADD32", /* name. */ false, /* partial_inplace. */ - 0, /* src_mask */ - ALL_ONES, /* dst_mask */ - false, /* pcrel_offset */ - BFD_RELOC_LARCH_ADD32, /* bfd_reloc_code_real_type */ - NULL, /* adjust_reloc_bits */ - NULL), /* larch_reloc_type_name */ - + 0, /* src_mask. */ + 0xffffffff, /* dst_mask. */ + false, /* pcrel_offset. */ + BFD_RELOC_LARCH_ADD32, /* bfd_reloc_code_real_type. */ + NULL, /* adjust_reloc_bits. */ + NULL), /* larch_reloc_type_name. */ + + /* 64-bit in-place addition, for local label subtraction. */ LOONGARCH_HOWTO (R_LARCH_ADD64, /* type (51). */ 0, /* rightshift. */ - 4, /* size. */ + 8, /* size. */ 64, /* bitsize. */ false, /* pc_relative. */ 0, /* bitpos. */ - complain_overflow_signed, /* complain_on_overflow. */ - bfd_elf_generic_reloc, /* special_function. */ + complain_overflow_dont, /* complain_on_overflow. */ + loongarch_elf_add_sub_reloc, /* special_function. */ "R_LARCH_ADD64", /* name. */ false, /* partial_inplace. */ - 0, /* src_mask */ - ALL_ONES, /* dst_mask */ - false, /* pcrel_offset */ - BFD_RELOC_LARCH_ADD64, /* bfd_reloc_code_real_type */ - NULL, /* adjust_reloc_bits */ - NULL), /* larch_reloc_type_name */ - + 0, /* src_mask. */ + ALL_ONES, /* dst_mask. */ + false, /* pcrel_offset. */ + BFD_RELOC_LARCH_ADD64, /* bfd_reloc_code_real_type. */ + NULL, /* adjust_reloc_bits. */ + NULL), /* larch_reloc_type_name. */ + + /* 8-bit in-place subtraction, for local label subtraction. */ LOONGARCH_HOWTO (R_LARCH_SUB8, /* type (52). */ 0, /* rightshift. */ - 2, /* size. */ + 1, /* size. */ 8, /* bitsize. */ false, /* pc_relative. */ 0, /* bitpos. */ - complain_overflow_signed, /* complain_on_overflow. */ - bfd_elf_generic_reloc, /* special_function. */ + complain_overflow_dont, /* complain_on_overflow. */ + loongarch_elf_add_sub_reloc, /* special_function. */ "R_LARCH_SUB8", /* name. */ false, /* partial_inplace. */ - 0, /* src_mask */ - ALL_ONES, /* dst_mask */ - false, /* pcrel_offset */ - BFD_RELOC_LARCH_SUB8, /* bfd_reloc_code_real_type */ - NULL, /* adjust_reloc_bits */ - NULL), /* larch_reloc_type_name */ - + 0, /* src_mask. */ + 0xff, /* dst_mask. */ + false, /* pcrel_offset. */ + BFD_RELOC_LARCH_SUB8, /* bfd_reloc_code_real_type. */ + NULL, /* adjust_reloc_bits. */ + NULL), /* larch_reloc_type_name. */ + + /* 16-bit in-place subtraction, for local label subtraction. */ LOONGARCH_HOWTO (R_LARCH_SUB16, /* type (53). */ 0, /* rightshift. */ 2, /* size. */ 16, /* bitsize. */ false, /* pc_relative. */ 0, /* bitpos. */ - complain_overflow_signed, /* complain_on_overflow. */ - bfd_elf_generic_reloc, /* special_function. */ + complain_overflow_dont, /* complain_on_overflow. */ + loongarch_elf_add_sub_reloc, /* special_function. */ "R_LARCH_SUB16", /* name. */ false, /* partial_inplace. */ - 0, /* src_mask */ - ALL_ONES, /* dst_mask */ - false, /* pcrel_offset */ - BFD_RELOC_LARCH_SUB16, /* bfd_reloc_code_real_type */ - NULL, /* adjust_reloc_bits */ - NULL), /* larch_reloc_type_name */ - + 0, /* src_mask. */ + 0xffff, /* dst_mask. */ + false, /* pcrel_offset. */ + BFD_RELOC_LARCH_SUB16, /* bfd_reloc_code_real_type. */ + NULL, /* adjust_reloc_bits. */ + NULL), /* larch_reloc_type_name. */ + + /* 24-bit in-place subtraction, for local label subtraction. */ LOONGARCH_HOWTO (R_LARCH_SUB24, /* type (54). */ 0, /* rightshift. */ - 2, /* size. */ + 3, /* size. */ 24, /* bitsize. */ false, /* pc_relative. */ 0, /* bitpos. */ - complain_overflow_signed, /* complain_on_overflow. */ - bfd_elf_generic_reloc, /* special_function. */ + complain_overflow_dont, /* complain_on_overflow. */ + loongarch_elf_add_sub_reloc, /* special_function. */ "R_LARCH_SUB24", /* name. */ false, /* partial_inplace. */ - 0, /* src_mask */ - ALL_ONES, /* dst_mask */ - false, /* pcrel_offset */ - BFD_RELOC_LARCH_SUB24, /* bfd_reloc_code_real_type */ - NULL, /* adjust_reloc_bits */ - NULL), /* larch_reloc_type_name */ - + 0, /* src_mask. */ + 0xffffff, /* dst_mask. */ + false, /* pcrel_offset. */ + BFD_RELOC_LARCH_SUB24, /* bfd_reloc_code_real_type. */ + NULL, /* adjust_reloc_bits. */ + NULL), /* larch_reloc_type_name. */ + + /* 32-bit in-place subtraction, for local label subtraction. */ LOONGARCH_HOWTO (R_LARCH_SUB32, /* type (55). */ 0, /* rightshift. */ - 2, /* size. */ + 4, /* size. */ 32, /* bitsize. */ false, /* pc_relative. */ 0, /* bitpos. */ - complain_overflow_signed, /* complain_on_overflow. */ - bfd_elf_generic_reloc, /* special_function. */ + complain_overflow_dont, /* complain_on_overflow. */ + loongarch_elf_add_sub_reloc, /* special_function. */ "R_LARCH_SUB32", /* name. */ false, /* partial_inplace. */ - 0, /* src_mask */ - ALL_ONES, /* dst_mask */ - false, /* pcrel_offset */ - BFD_RELOC_LARCH_SUB32, /* bfd_reloc_code_real_type */ - NULL, /* adjust_reloc_bits */ - NULL), /* larch_reloc_type_name */ - + 0, /* src_mask. */ + 0xffffffff, /* dst_mask. */ + false, /* pcrel_offset. */ + BFD_RELOC_LARCH_SUB32, /* bfd_reloc_code_real_type. */ + NULL, /* adjust_reloc_bits. */ + NULL), /* larch_reloc_type_name. */ + + /* 64-bit in-place subtraction, for local label subtraction. */ LOONGARCH_HOWTO (R_LARCH_SUB64, /* type (56). */ 0, /* rightshift. */ - 4, /* size. */ + 8, /* size. */ 64, /* bitsize. */ false, /* pc_relative. */ 0, /* bitpos. */ - complain_overflow_signed, /* complain_on_overflow. */ - bfd_elf_generic_reloc, /* special_function. */ + complain_overflow_dont, /* complain_on_overflow. */ + loongarch_elf_add_sub_reloc, /* special_function. */ "R_LARCH_SUB64", /* name. */ false, /* partial_inplace. */ - 0, /* src_mask */ - ALL_ONES, /* dst_mask */ - false, /* pcrel_offset */ - BFD_RELOC_LARCH_SUB64, /* bfd_reloc_code_real_type */ - NULL, /* adjust_reloc_bits */ - NULL), /* larch_reloc_type_name */ + 0, /* src_mask. */ + ALL_ONES, /* dst_mask. */ + false, /* pcrel_offset. */ + BFD_RELOC_LARCH_SUB64, /* bfd_reloc_code_real_type. */ + NULL, /* adjust_reloc_bits. */ + NULL), /* larch_reloc_type_name. */ LOONGARCH_HOWTO (R_LARCH_GNU_VTINHERIT, /* type (57). */ 0, /* rightshift. */ @@ -742,12 +756,12 @@ static loongarch_reloc_howto_type loongarch_howto_table[] = bfd_elf_generic_reloc, /* special_function. */ "R_LARCH_B16", /* name. */ false, /* partial_inplace. */ - 0x3fffc00, /* src_mask */ - 0x3fffc00, /* dst_mask */ - false, /* pcrel_offset */ - BFD_RELOC_LARCH_B16, /* bfd_reloc_code_real_type */ - reloc_bits_b16, /* adjust_reloc_bits */ - "b16"), /* larch_reloc_type_name */ + 0, /* src_mask. */ + 0x3fffc00, /* dst_mask. */ + false, /* pcrel_offset. */ + BFD_RELOC_LARCH_B16, /* bfd_reloc_code_real_type. */ + reloc_sign_bits, /* adjust_reloc_bits. */ + "b16"), /* larch_reloc_type_name. */ LOONGARCH_HOWTO (R_LARCH_B21, /* type (65). */ 2, /* rightshift. */ @@ -759,12 +773,12 @@ static loongarch_reloc_howto_type loongarch_howto_table[] = bfd_elf_generic_reloc, /* special_function. */ "R_LARCH_B21", /* name. */ false, /* partial_inplace. */ - 0xfc0003e0, /* src_mask */ - 0xfc0003e0, /* dst_mask */ - false, /* pcrel_offset */ - BFD_RELOC_LARCH_B21, /* bfd_reloc_code_real_type */ - reloc_bits_b21, /* adjust_reloc_bits */ - "b21"), /* larch_reloc_type_name */ + 0, /* src_mask. */ + 0x3fffc1f, /* dst_mask. */ + false, /* pcrel_offset. */ + BFD_RELOC_LARCH_B21, /* bfd_reloc_code_real_type. */ + reloc_sign_bits, /* adjust_reloc_bits. */ + "b21"), /* larch_reloc_type_name. */ LOONGARCH_HOWTO (R_LARCH_B26, /* type (66). */ 2, /* rightshift. */ @@ -776,12 +790,12 @@ static loongarch_reloc_howto_type loongarch_howto_table[] = bfd_elf_generic_reloc, /* special_function. */ "R_LARCH_B26", /* name. */ false, /* partial_inplace. */ - 0, /* src_mask */ - 0x03ffffff, /* dst_mask */ - false, /* pcrel_offset */ - BFD_RELOC_LARCH_B26, /* bfd_reloc_code_real_type */ - reloc_bits_b26, /* adjust_reloc_bits */ - "b26"), /* larch_reloc_type_name */ + 0, /* src_mask. */ + 0x03ffffff, /* dst_mask. */ + false, /* pcrel_offset. */ + BFD_RELOC_LARCH_B26, /* bfd_reloc_code_real_type. */ + reloc_sign_bits, /* adjust_reloc_bits. */ + "b26"), /* larch_reloc_type_name. */ LOONGARCH_HOWTO (R_LARCH_ABS_HI20, /* type (67). */ 12, /* rightshift. */ @@ -1078,7 +1092,7 @@ static loongarch_reloc_howto_type loongarch_howto_table[] = 12, /* bitsize. */ false, /* pc_relative. */ 10, /* bitpos. */ - complain_overflow_signed, /* complain_on_overflow. */ + complain_overflow_unsigned, /* complain_on_overflow. */ bfd_elf_generic_reloc, /* special_function. */ "R_LARCH_TLS_LE_LO12", /* name. */ false, /* partial_inplace. */ @@ -1146,7 +1160,7 @@ static loongarch_reloc_howto_type loongarch_howto_table[] = 12, /* bitsize. */ false, /* pc_relative. */ 10, /* bitpos. */ - complain_overflow_unsigned, /* complain_on_overflow. */ + complain_overflow_signed, /* complain_on_overflow. */ bfd_elf_generic_reloc, /* special_function. */ "R_LARCH_TLS_IE_PC_LO12", /* name. */ false, /* partial_inplace. */ @@ -1191,7 +1205,7 @@ static loongarch_reloc_howto_type loongarch_howto_table[] = reloc_bits, /* adjust_reloc_bits */ "ie64_pc_hi12"), /* larch_reloc_type_name */ - LOONGARCH_HOWTO (R_LARCH_TLS_IE_HI20, /* type (91). */ + LOONGARCH_HOWTO (R_LARCH_TLS_IE_HI20, /* type (91). */ 12, /* rightshift. */ 2, /* size. */ 20, /* bitsize. */ @@ -1327,13 +1341,14 @@ static loongarch_reloc_howto_type loongarch_howto_table[] = reloc_bits, /* adjust_reloc_bits */ "gd_hi20"), /* larch_reloc_type_name */ + /* 32-bit PC relative. */ LOONGARCH_HOWTO (R_LARCH_32_PCREL, /* type (99). */ 0, /* rightshift. */ 2, /* size. */ 32, /* bitsize. */ true, /* pc_relative. */ 0, /* bitpos. */ - complain_overflow_dont, /* complain_on_overflow. */ + complain_overflow_signed, /* complain_on_overflow. */ bfd_elf_generic_reloc, /* special_function. */ "R_LARCH_32_PCREL", /* name. */ false, /* partial_inplace. */ @@ -1344,6 +1359,7 @@ static loongarch_reloc_howto_type loongarch_howto_table[] = NULL, /* adjust_reloc_bits */ NULL), /* larch_reloc_type_name */ + /* The paired relocation may be relaxed. */ LOONGARCH_HOWTO (R_LARCH_RELAX, /* type (100). */ 0, /* rightshift */ 0, /* size */ @@ -1361,6 +1377,176 @@ static loongarch_reloc_howto_type loongarch_howto_table[] = NULL, /* adjust_reloc_bits */ NULL), /* larch_reloc_type_name */ + /* Delete relaxed instruction. */ + LOONGARCH_HOWTO (R_LARCH_DELETE, /* type (101). */ + 0, /* rightshift. */ + 0, /* size. */ + 0, /* bitsize. */ + false, /* pc_relative. */ + 0, /* bitpos. */ + complain_overflow_dont, /* complain_on_overflow. */ + bfd_elf_generic_reloc, /* special_function. */ + "R_LARCH_DELETE", /* name. */ + false, /* partial_inplace. */ + 0, /* src_mask. */ + 0, /* dst_mask. */ + false, /* pcrel_offset. */ + BFD_RELOC_LARCH_DELETE, /* bfd_reloc_code_real_type. */ + NULL, /* adjust_reloc_bits. */ + NULL), /* larch_reloc_type_name. */ + + /* Indicates an alignment statement. The addend field encodes how many + bytes of NOPs follow the statement. The desired alignment is the + addend rounded up to the next power of two. */ + LOONGARCH_HOWTO (R_LARCH_ALIGN, /* type (102). */ + 0, /* rightshift. */ + 0, /* size. */ + 0, /* bitsize. */ + false, /* pc_relative. */ + 0, /* bitpos. */ + complain_overflow_dont, /* complain_on_overflow. */ + bfd_elf_generic_reloc, /* special_function. */ + "R_LARCH_ALIGN", /* name. */ + false, /* partial_inplace. */ + 0, /* src_mask. */ + 0, /* dst_mask. */ + false, /* pcrel_offset. */ + BFD_RELOC_LARCH_ALIGN, /* bfd_reloc_code_real_type. */ + NULL, /* adjust_reloc_bits. */ + NULL), /* larch_reloc_type_name. */ + + /* pcala_hi20 + pcala_lo12 relaxed to pcrel20_s2. */ + LOONGARCH_HOWTO (R_LARCH_PCREL20_S2, /* type (103). */ + 2, /* rightshift. */ + 2, /* size. */ + 20, /* bitsize. */ + false, /* pc_relative. */ + 5, /* bitpos. */ + complain_overflow_signed, /* complain_on_overflow. */ + bfd_elf_generic_reloc, /* special_function. */ + "R_LARCH_PCREL20_S2", /* name. */ + false, /* partial_inplace. */ + 0, /* src_mask. */ + 0x1ffffe0, /* dst_mask. */ + false, /* pcrel_offset. */ + BFD_RELOC_LARCH_PCREL20_S2, /* bfd_reloc_code_real_type. */ + reloc_sign_bits, /* adjust_reloc_bits. */ + NULL), /* larch_reloc_type_name. */ + + /* Canonical Frame Address. */ + LOONGARCH_HOWTO (R_LARCH_CFA, /* type (104). */ + 0, /* rightshift. */ + 0, /* size. */ + 0, /* bitsize. */ + false, /* pc_relative. */ + 0, /* bitpos. */ + complain_overflow_dont, /* complain_on_overflow. */ + bfd_elf_generic_reloc, /* special_function. */ + "R_LARCH_CFA", /* name. */ + false, /* partial_inplace. */ + 0, /* src_mask. */ + 0, /* dst_mask. */ + false, /* pcrel_offset. */ + BFD_RELOC_LARCH_CFA, /* bfd_reloc_code_real_type. */ + NULL, /* adjust_reloc_bits. */ + NULL), /* larch_reloc_type_name. */ + + /* 6-bit in-place addition, for local label subtraction + to calculate DW_CFA_advance_loc. */ + LOONGARCH_HOWTO (R_LARCH_ADD6, /* type (105). */ + 0, /* rightshift. */ + 1, /* size. */ + 8, /* bitsize. */ + false, /* pc_relative. */ + 0, /* bitpos. */ + complain_overflow_dont, /* complain_on_overflow. */ + loongarch_elf_add_sub_reloc, /* special_function. */ + "R_LARCH_ADD6", /* name. */ + false, /* partial_inplace. */ + 0, /* src_mask. */ + 0x3f, /* dst_mask. */ + false, /* pcrel_offset. */ + BFD_RELOC_LARCH_ADD6, /* bfd_reloc_code_real_type. */ + reloc_bits, /* adjust_reloc_bits. */ + NULL), /* larch_reloc_type_name. */ + + /* 6-bit in-place subtraction, for local label subtraction + to calculate DW_CFA_advance_loc. */ + LOONGARCH_HOWTO (R_LARCH_SUB6, /* type (106). */ + 0, /* rightshift. */ + 1, /* size. */ + 8, /* bitsize. */ + false, /* pc_relative. */ + 0, /* bitpos. */ + complain_overflow_dont, /* complain_on_overflow. */ + loongarch_elf_add_sub_reloc, /* special_function. */ + "R_LARCH_SUB6", /* name. */ + false, /* partial_inplace. */ + 0, /* src_mask. */ + 0x3f, /* dst_mask. */ + false, /* pcrel_offset. */ + BFD_RELOC_LARCH_SUB6, /* bfd_reloc_code_real_type. */ + reloc_bits, /* adjust_reloc_bits. */ + NULL), /* larch_reloc_type_name. */ + + /* The length of unsigned-leb128 is variable, just assume the + size is one byte here. + uleb128 in-place addition, for local label subtraction. */ + LOONGARCH_HOWTO (R_LARCH_ADD_ULEB128, /* type (107). */ + 0, /* rightshift. */ + 1, /* size. */ + 0, /* bitsize. */ + false, /* pc_relative. */ + 0, /* bitpos. */ + complain_overflow_dont, /* complain_on_overflow. */ + loongarch_elf_add_sub_reloc_uleb128, /* special_function. */ + "R_LARCH_ADD_ULEB128", /* name. */ + false, /* partial_inplace. */ + 0, /* src_mask. */ + 0, /* dst_mask. */ + false, /* pcrel_offset. */ + BFD_RELOC_LARCH_ADD_ULEB128, /* bfd_reloc_code_real_type. */ + NULL, /* adjust_reloc_bits. */ + NULL), /* larch_reloc_type_name. */ + + /* The length of unsigned-leb128 is variable, just assume the + size is one byte here. + uleb128 in-place subtraction, for local label subtraction. */ + LOONGARCH_HOWTO (R_LARCH_SUB_ULEB128, /* type (108). */ + 0, /* rightshift. */ + 1, /* size. */ + 0, /* bitsize. */ + false, /* pc_relative. */ + 0, /* bitpos. */ + complain_overflow_dont, /* complain_on_overflow. */ + loongarch_elf_add_sub_reloc_uleb128, /* special_function. */ + "R_LARCH_SUB_ULEB128", /* name. */ + false, /* partial_inplace. */ + 0, /* src_mask. */ + 0, /* dst_mask. */ + false, /* pcrel_offset. */ + BFD_RELOC_LARCH_SUB_ULEB128, /* bfd_reloc_code_real_type. */ + NULL, /* adjust_reloc_bits. */ + NULL), /* larch_reloc_type_name. */ + + /* 64-bit PC relative. */ + LOONGARCH_HOWTO (R_LARCH_64_PCREL, /* type (109). */ + 0, /* rightshift. */ + 8, /* size. */ + 64, /* bitsize. */ + true, /* pc_relative. */ + 0, /* bitpos. */ + complain_overflow_signed, /* complain_on_overflow. */ + bfd_elf_generic_reloc, /* special_function. */ + "R_LARCH_64_PCREL", /* name. */ + false, /* partial_inplace. */ + 0, /* src_mask */ + 0xffffffffffffffff, /* dst_mask */ + false, /* pcrel_offset */ + BFD_RELOC_LARCH_64_PCREL, /* bfd_reloc_code_real_type */ + NULL, /* adjust_reloc_bits */ + NULL), /* larch_reloc_type_name */ + }; reloc_howto_type * @@ -1464,13 +1650,19 @@ loongarch_larch_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED, BFD_RELOC_LARCH_SOP_POP_32_S_10_16 BFD_RELOC_LARCH_SOP_POP_32_S_5_20 BFD_RELOC_LARCH_SOP_POP_32_U. */ + static bool -reloc_bits (reloc_howto_type *howto, bfd_vma *fix_val) +reloc_bits (bfd *abfd ATTRIBUTE_UNUSED, + reloc_howto_type *howto, + bfd_vma *fix_val) { - bfd_signed_vma val = ((bfd_signed_vma)(*fix_val)) >> howto->rightshift; + bfd_signed_vma val = (bfd_signed_vma)(*fix_val); + bfd_signed_vma mask = ((bfd_signed_vma)0x1 << howto->bitsize) - 1; + + val = val >> howto->rightshift; /* Perform insn bits field. */ - val = val & (((bfd_vma)0x1 << howto->bitsize) - 1); + val = val & mask; val <<= howto->bitpos; *fix_val = (bfd_vma)val; @@ -1478,141 +1670,206 @@ reloc_bits (reloc_howto_type *howto, bfd_vma *fix_val) return true; } -/* Adjust val to perform insn - R_LARCH_SOP_POP_32_S_10_16_S2 - R_LARCH_B16. */ static bool -reloc_bits_b16 (reloc_howto_type *howto, bfd_vma *fix_val) +reloc_sign_bits (bfd *abfd, reloc_howto_type *howto, bfd_vma *fix_val) { if (howto->complain_on_overflow != complain_overflow_signed) return false; - bfd_signed_vma val = *fix_val; + bfd_signed_vma val = (bfd_signed_vma)(*fix_val); - /* Judge whether 4 bytes align. */ - if (val & ((0x1UL << howto->rightshift) - 1)) - return false; + /* Check alignment. FIXME: if rightshift is not alingment. */ + if (howto->rightshift + && (val & ((((bfd_signed_vma) 1) << howto->rightshift) - 1))) + { + (*_bfd_error_handler) (_("%pB: relocation %s right shift %d error 0x%lx"), + abfd, howto->name, howto->rightshift, (long) val); + bfd_set_error (bfd_error_bad_value); + return false; + } - int bitsize = howto->bitsize + howto->rightshift; - bfd_signed_vma sig_bit = (val >> (bitsize - 1)) & 0x1; + bfd_signed_vma mask = ((bfd_signed_vma)0x1 << (howto->bitsize + + howto->rightshift - 1)) - 1; - /* If val < 0, sign bit is 1. */ - if (sig_bit) + /* Positive number: high part is all 0; + Negative number: if high part is not all 0, high part must be all 1. + high part: from sign bit to highest bit. */ + if ((val & ~mask) && ((val & ~mask) != ~mask)) { - /* Signed bits is 1. */ - if ((LARCH_RELOC_BFD_VMA_BIT_MASK (bitsize - 1) & val) - != LARCH_RELOC_BFD_VMA_BIT_MASK (bitsize - 1)) - return false; + (*_bfd_error_handler) (_("%pB: relocation %s overflow 0x%lx"), + abfd, howto->name, (long) val); + bfd_set_error (bfd_error_bad_value); + return false; } - else + + val = val >> howto->rightshift; + /* can delete? */ + mask = ((bfd_signed_vma)0x1 << howto->bitsize) - 1; + val = val & mask; + + switch (howto->type) { - /* Signed bits is 0. */ - if (LARCH_RELOC_BFD_VMA_BIT_MASK (bitsize) & val) - return false; + case R_LARCH_SOP_POP_32_S_0_10_10_16_S2: + case R_LARCH_B26: + /* Perform insn bits field. 25:16>>16, 15:0<<10. */ + val = ((val & 0xffff) << 10) | ((val >> 16) & 0x3ff); + break; + case R_LARCH_B21: + val = ((val & 0xffff) << 10) | ((val >> 16) & 0x1f); + break; + default: + val <<= howto->bitpos; + break; } - /* Perform insn bits field. */ - val >>= howto->rightshift; - val = val & (((bfd_vma)0x1 << howto->bitsize) - 1); - val <<= howto->bitpos; - *fix_val = val; - return true; } -/* Reloc type : - R_LARCH_SOP_POP_32_S_0_5_10_16_S2 - R_LARCH_B21. */ -static bool -reloc_bits_b21 (reloc_howto_type *howto, - bfd_vma *fix_val) +bool +loongarch_adjust_reloc_bitsfield (bfd *abfd, reloc_howto_type *howto, + bfd_vma *fix_val) { - if (howto->complain_on_overflow != complain_overflow_signed) - return false; - - bfd_signed_vma val = *fix_val; - - if (val & ((0x1UL << howto->rightshift) - 1)) - return false; + BFD_ASSERT (((loongarch_reloc_howto_type *)howto)->adjust_reloc_bits); + return ((loongarch_reloc_howto_type *) + howto)->adjust_reloc_bits (abfd, howto, fix_val); +} - int bitsize = howto->bitsize + howto->rightshift; - bfd_signed_vma sig_bit = (val >> (bitsize - 1)) & 0x1; +static bfd_reloc_status_type +loongarch_elf_add_sub_reloc (bfd *abfd, + arelent *reloc_entry, + asymbol *symbol, + void *data, + asection *input_section, + bfd *output_bfd, + char **error_message ATTRIBUTE_UNUSED) +{ + reloc_howto_type *howto = reloc_entry->howto; + bfd_vma relocation; - /* If val < 0. */ - if (sig_bit) + if (output_bfd != NULL + && (symbol->flags & BSF_SECTION_SYM) == 0 + && (!reloc_entry->howto->partial_inplace || reloc_entry->addend == 0)) { - if ((LARCH_RELOC_BFD_VMA_BIT_MASK (bitsize - 1) & val) - != LARCH_RELOC_BFD_VMA_BIT_MASK (bitsize - 1)) - return false; + reloc_entry->address += input_section->output_offset; + return bfd_reloc_ok; } - else - { - if (LARCH_RELOC_BFD_VMA_BIT_MASK (bitsize) & val) - return false; - } - - /* Perform insn bits field. */ - val >>= howto->rightshift; - val = val & (((bfd_vma)0x1 << howto->bitsize) - 1); - /* Perform insn bits field. 15:0<<10, 20:16>>16. */ - val = ((val & 0xffff) << 10) | ((val >> 16) & 0x1f); + if (output_bfd != NULL) + return bfd_reloc_continue; - *fix_val = val; + relocation = symbol->value + symbol->section->output_section->vma + + symbol->section->output_offset + reloc_entry->addend; - return true; -} + bfd_size_type octets = reloc_entry->address + * bfd_octets_per_byte (abfd, input_section); + if (!bfd_reloc_offset_in_range (reloc_entry->howto, abfd, + input_section, octets)) + return bfd_reloc_outofrange; -/* Reloc type: - R_LARCH_SOP_POP_32_S_0_10_10_16_S2 - R_LARCH_B26. */ -static bool -reloc_bits_b26 (reloc_howto_type *howto, - bfd_vma *fix_val) -{ - /* Return false if overflow. */ - if (howto->complain_on_overflow != complain_overflow_signed) - return false; + bfd_vma old_value = bfd_get (howto->bitsize, abfd, + data + reloc_entry->address); - bfd_signed_vma val = *fix_val; + switch (howto->type) + { + case R_LARCH_ADD6: + case R_LARCH_ADD8: + case R_LARCH_ADD16: + case R_LARCH_ADD32: + case R_LARCH_ADD64: + relocation = old_value + relocation; + break; + + case R_LARCH_SUB6: + case R_LARCH_SUB8: + case R_LARCH_SUB16: + case R_LARCH_SUB32: + case R_LARCH_SUB64: + relocation = old_value - relocation; + break; + } - if (val & ((0x1UL << howto->rightshift) - 1)) - return false; + bfd_put (howto->bitsize, abfd, relocation, data + reloc_entry->address); - int bitsize = howto->bitsize + howto->rightshift; - bfd_signed_vma sig_bit = (val >> (bitsize - 1)) & 0x1; + return bfd_reloc_ok; +} - /* If val < 0. */ - if (sig_bit) - { - if ((LARCH_RELOC_BFD_VMA_BIT_MASK (bitsize - 1) & val) - != LARCH_RELOC_BFD_VMA_BIT_MASK (bitsize - 1)) - return false; - } - else +static bfd_reloc_status_type +loongarch_elf_add_sub_reloc_uleb128 (bfd *abfd, + arelent *reloc_entry, + asymbol *symbol, + void *data, + asection *input_section, + bfd *output_bfd, + char **error_message ATTRIBUTE_UNUSED) +{ + reloc_howto_type *howto = reloc_entry->howto; + bfd_vma relocation; + + if (output_bfd != NULL + && (symbol->flags & BSF_SECTION_SYM) == 0 + && (!reloc_entry->howto->partial_inplace || reloc_entry->addend == 0)) + { + reloc_entry->address += input_section->output_offset; + return bfd_reloc_ok; + } + + if (output_bfd != NULL) + return bfd_reloc_continue; + + relocation = symbol->value + symbol->section->output_section->vma + + symbol->section->output_offset + reloc_entry->addend; + + bfd_size_type octets = reloc_entry->address + * bfd_octets_per_byte (abfd, input_section); + if (!bfd_reloc_offset_in_range (reloc_entry->howto, abfd, + input_section, octets)) + return bfd_reloc_outofrange; + + unsigned int len = 0; + bfd_byte *p = data + reloc_entry->address; + bfd_vma old_value = _bfd_read_unsigned_leb128 (abfd, p, &len); + + switch (howto->type) { - if (LARCH_RELOC_BFD_VMA_BIT_MASK (bitsize) & val) - return false; - } - - /* Perform insn bits field. */ - val >>= howto->rightshift; - val = val & (((bfd_vma)0x1 << howto->bitsize) - 1); + case R_LARCH_ADD_ULEB128: + relocation = old_value + relocation; + break; - /* Perform insn bits field. 25:16>>16, 15:0<<10. */ - val = ((val & 0xffff) << 10) | ((val >> 16) & 0x3ff); + case R_LARCH_SUB_ULEB128: + relocation = old_value - relocation; + break; + } - *fix_val = val; + bfd_vma mask = (1 << (7 * len)) - 1; + relocation = relocation & mask; + loongarch_write_unsigned_leb128 (p, len, relocation); + return bfd_reloc_ok; +} - return true; +/* Write VALUE in uleb128 format to P. + LEN is the uleb128 value length. + Return a pointer to the byte following the last byte that was written. */ +bfd_byte * +loongarch_write_unsigned_leb128 (bfd_byte *p, unsigned int len, bfd_vma value) +{ + bfd_byte c; + do + { + c = value & 0x7f; + if (len > 1) + c |= 0x80; + *(p++) = c; + value >>= 7; + len--; + } + while (len); + return p; } -bool -loongarch_adjust_reloc_bitsfield (reloc_howto_type *howto, - bfd_vma *fix_val) +int loongarch_get_uleb128_length (bfd_byte *buf) { - BFD_ASSERT (((loongarch_reloc_howto_type *)howto)->adjust_reloc_bits); - return ((loongarch_reloc_howto_type *) - howto)->adjust_reloc_bits(howto, fix_val); + unsigned int len = 0; + _bfd_read_unsigned_leb128 (NULL, buf, &len); + return len; } diff --git a/bfd/elfxx-loongarch.h b/bfd/elfxx-loongarch.h index 7b8a7213..566c2a6b 100644 --- a/bfd/elfxx-loongarch.h +++ b/bfd/elfxx-loongarch.h @@ -34,7 +34,17 @@ extern bfd_reloc_code_real_type loongarch_larch_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED, const char *l_r_name); -bool loongarch_adjust_reloc_bitsfield (reloc_howto_type *howto, bfd_vma *fix_val); +bool +loongarch_adjust_reloc_bitsfield (bfd *, reloc_howto_type *, bfd_vma *); +void +bfd_elf32_loongarch_set_data_segment_info (struct bfd_link_info *, int *); +void +bfd_elf64_loongarch_set_data_segment_info (struct bfd_link_info *, int *); + +bfd_byte * +loongarch_write_unsigned_leb128 (bfd_byte *p, unsigned int len, bfd_vma value); + +int loongarch_get_uleb128_length (bfd_byte *buf); /* TRUE if this is a PLT reference to a local IFUNC. */ #define PLT_LOCAL_IFUNC_P(INFO, H) \ diff --git a/bfd/libbfd.h b/bfd/libbfd.h index 1b689f2d..67324ba8 100644 --- a/bfd/libbfd.h +++ b/bfd/libbfd.h @@ -3493,6 +3493,15 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@", "BFD_RELOC_LARCH_TLS_GD_HI20", "BFD_RELOC_LARCH_32_PCREL", "BFD_RELOC_LARCH_RELAX", + "BFD_RELOC_LARCH_DELETE", + "BFD_RELOC_LARCH_ALIGN", + "BFD_RELOC_LARCH_PCREL20_S2", + "BFD_RELOC_LARCH_CFA", + "BFD_RELOC_LARCH_ADD6", + "BFD_RELOC_LARCH_SUB6", + "BFD_RELOC_LARCH_ADD_ULEB128", + "BFD_RELOC_LARCH_SUB_ULEB128", + "BFD_RELOC_LARCH_64_PCREL", "@@overflow: BFD_RELOC_UNUSED@@", }; #endif diff --git a/bfd/libpei.h b/bfd/libpei.h index 26589e8e..4e6a3094 100644 --- a/bfd/libpei.h +++ b/bfd/libpei.h @@ -310,6 +310,41 @@ #define _bfd_XXi_write_codeview_record _bfd_peAArch64i_write_codeview_record #define _bfd_XXi_slurp_codeview_record _bfd_peAArch64i_slurp_codeview_record +#elif defined COFF_WITH_peLoongArch64 + +#define GET_OPTHDR_IMAGE_BASE H_GET_64 +#define PUT_OPTHDR_IMAGE_BASE H_PUT_64 +#define GET_OPTHDR_SIZE_OF_STACK_RESERVE H_GET_64 +#define PUT_OPTHDR_SIZE_OF_STACK_RESERVE H_PUT_64 +#define GET_OPTHDR_SIZE_OF_STACK_COMMIT H_GET_64 +#define PUT_OPTHDR_SIZE_OF_STACK_COMMIT H_PUT_64 +#define GET_OPTHDR_SIZE_OF_HEAP_RESERVE H_GET_64 +#define PUT_OPTHDR_SIZE_OF_HEAP_RESERVE H_PUT_64 +#define GET_OPTHDR_SIZE_OF_HEAP_COMMIT H_GET_64 +#define PUT_OPTHDR_SIZE_OF_HEAP_COMMIT H_PUT_64 +#define GET_PDATA_ENTRY bfd_get_32 + +#define _bfd_XX_bfd_copy_private_bfd_data_common _bfd_peLoongArch64_bfd_copy_private_bfd_data_common +#define _bfd_XX_bfd_copy_private_section_data _bfd_peLoongArch64_bfd_copy_private_section_data +#define _bfd_XX_get_symbol_info _bfd_peLoongArch64_get_symbol_info +#define _bfd_XX_only_swap_filehdr_out _bfd_peLoongArch64_only_swap_filehdr_out +#define _bfd_XX_print_private_bfd_data_common _bfd_peLoongArch64_print_private_bfd_data_common +#define _bfd_XXi_final_link_postscript _bfd_peLoongArch64i_final_link_postscript +#define _bfd_XXi_only_swap_filehdr_out _bfd_peLoongArch64i_only_swap_filehdr_out +#define _bfd_XXi_swap_aouthdr_in _bfd_peLoongArch64i_swap_aouthdr_in +#define _bfd_XXi_swap_aouthdr_out _bfd_peLoongArch64i_swap_aouthdr_out +#define _bfd_XXi_swap_aux_in _bfd_peLoongArch64i_swap_aux_in +#define _bfd_XXi_swap_aux_out _bfd_peLoongArch64i_swap_aux_out +#define _bfd_XXi_swap_lineno_in _bfd_peLoongArch64i_swap_lineno_in +#define _bfd_XXi_swap_lineno_out _bfd_peLoongArch64i_swap_lineno_out +#define _bfd_XXi_swap_scnhdr_out _bfd_peLoongArch64i_swap_scnhdr_out +#define _bfd_XXi_swap_sym_in _bfd_peLoongArch64i_swap_sym_in +#define _bfd_XXi_swap_sym_out _bfd_peLoongArch64i_swap_sym_out +#define _bfd_XXi_swap_debugdir_in _bfd_peLoongArch64i_swap_debugdir_in +#define _bfd_XXi_swap_debugdir_out _bfd_peLoongArch64i_swap_debugdir_out +#define _bfd_XXi_write_codeview_record _bfd_peLoongArch64i_write_codeview_record +#define _bfd_XXi_slurp_codeview_record _bfd_peLoongArch64i_slurp_codeview_record + #else /* !COFF_WITH_pep */ #define GET_OPTHDR_IMAGE_BASE H_GET_32 @@ -405,5 +440,6 @@ bool _bfd_pe_print_ce_compressed_pdata (bfd *, void *); bool _bfd_pe64_print_ce_compressed_pdata (bfd *, void *); bool _bfd_pex64_print_ce_compressed_pdata (bfd *, void *); bool _bfd_peAArch64_print_ce_compressed_pdata (bfd *, void *); +bool _bfd_peLoongArch64_print_ce_compressed_pdata (bfd *, void *); bool _bfd_pep_print_ce_compressed_pdata (bfd *, void *); diff --git a/bfd/peXXigen.c b/bfd/peXXigen.c index 1bfd6c89..b0b799f2 100644 --- a/bfd/peXXigen.c +++ b/bfd/peXXigen.c @@ -60,9 +60,9 @@ on this code has a chance of getting something accomplished without wasting too much time. */ -/* This expands into COFF_WITH_pe, COFF_WITH_pep, COFF_WITH_pex64 or - COFF_WITH_peAArch64 depending on whether we're compiling for straight - PE or PE+. */ +/* This expands into COFF_WITH_pe, COFF_WITH_pep, COFF_WITH_pex64, + COFF_WITH_peAArch64 or COFF_WITH_peLoongArch64 depending on whether we're + compiling for straight PE or PE+. */ #define COFF_WITH_XX #include "sysdep.h" @@ -86,6 +86,8 @@ # include "coff/ia64.h" #elif defined COFF_WITH_peAArch64 # include "coff/aarch64.h" +#elif defined COFF_WITH_peLoongArch64 +# include "coff/loongarch64.h" #else # include "coff/i386.h" #endif @@ -95,7 +97,7 @@ #include "libpei.h" #include "safe-ctype.h" -#if defined COFF_WITH_pep || defined COFF_WITH_pex64 || defined COFF_WITH_peAArch64 +#if defined COFF_WITH_pep || defined COFF_WITH_pex64 || defined COFF_WITH_peAArch64 || defined COFF_WITH_peLoongArch64 # undef AOUTSZ # define AOUTSZ PEPAOUTSZ # define PEAOUTHDR PEPAOUTHDR @@ -472,7 +474,7 @@ _bfd_XXi_swap_aouthdr_in (bfd * abfd, aouthdr_int->text_start = GET_AOUTHDR_TEXT_START (abfd, aouthdr_ext->text_start); -#if !defined(COFF_WITH_pep) && !defined(COFF_WITH_pex64) && !defined(COFF_WITH_peAArch64) +#if !defined(COFF_WITH_pep) && !defined(COFF_WITH_pex64) && !defined(COFF_WITH_peAArch64) && !defined(COFF_WITH_peLoongArch64) /* PE32+ does not have data_start member! */ aouthdr_int->data_start = GET_AOUTHDR_DATA_START (abfd, aouthdr_ext->data_start); @@ -558,7 +560,7 @@ _bfd_XXi_swap_aouthdr_in (bfd * abfd, if (aouthdr_int->entry) { aouthdr_int->entry += a->ImageBase; -#if !defined(COFF_WITH_pep) && !defined(COFF_WITH_pex64) && !defined(COFF_WITH_peAArch64) +#if !defined(COFF_WITH_pep) && !defined(COFF_WITH_pex64) && !defined(COFF_WITH_peAArch64) && !defined(COFF_WITH_peLoongArch64) aouthdr_int->entry &= 0xffffffff; #endif } @@ -566,12 +568,12 @@ _bfd_XXi_swap_aouthdr_in (bfd * abfd, if (aouthdr_int->tsize) { aouthdr_int->text_start += a->ImageBase; -#if !defined(COFF_WITH_pep) && !defined(COFF_WITH_pex64) && !defined(COFF_WITH_peAArch64) +#if !defined(COFF_WITH_pep) && !defined(COFF_WITH_pex64) && !defined(COFF_WITH_peAArch64) && !defined(COFF_WITH_peLoongArch64) aouthdr_int->text_start &= 0xffffffff; #endif } -#if !defined(COFF_WITH_pep) && !defined(COFF_WITH_pex64) && !defined(COFF_WITH_peAArch64) +#if !defined(COFF_WITH_pep) && !defined(COFF_WITH_pex64) && !defined(COFF_WITH_peAArch64) && !defined(COFF_WITH_peLoongArch64) /* PE32+ does not have data_start member! */ if (aouthdr_int->dsize) { @@ -631,7 +633,7 @@ _bfd_XXi_swap_aouthdr_out (bfd * abfd, void * in, void * out) if (aouthdr_in->tsize) { aouthdr_in->text_start -= ib; -#if !defined(COFF_WITH_pep) && !defined(COFF_WITH_pex64) && !defined(COFF_WITH_peAArch64) +#if !defined(COFF_WITH_pep) && !defined(COFF_WITH_pex64) && !defined(COFF_WITH_peAArch64) && !defined(COFF_WITH_peLoongArch64) aouthdr_in->text_start &= 0xffffffff; #endif } @@ -639,7 +641,7 @@ _bfd_XXi_swap_aouthdr_out (bfd * abfd, void * in, void * out) if (aouthdr_in->dsize) { aouthdr_in->data_start -= ib; -#if !defined(COFF_WITH_pep) && !defined(COFF_WITH_pex64) && !defined(COFF_WITH_peAArch64) +#if !defined(COFF_WITH_pep) && !defined(COFF_WITH_pex64) && !defined(COFF_WITH_peAArch64) && !defined(COFF_WITH_peLoongArch64) aouthdr_in->data_start &= 0xffffffff; #endif } @@ -647,7 +649,7 @@ _bfd_XXi_swap_aouthdr_out (bfd * abfd, void * in, void * out) if (aouthdr_in->entry) { aouthdr_in->entry -= ib; -#if !defined(COFF_WITH_pep) && !defined(COFF_WITH_pex64) && !defined(COFF_WITH_peAArch64) +#if !defined(COFF_WITH_pep) && !defined(COFF_WITH_pex64) && !defined(COFF_WITH_peAArch64) && !defined(COFF_WITH_peLoongArch64) aouthdr_in->entry &= 0xffffffff; #endif } @@ -751,7 +753,7 @@ _bfd_XXi_swap_aouthdr_out (bfd * abfd, void * in, void * out) PUT_AOUTHDR_TEXT_START (abfd, aouthdr_in->text_start, aouthdr_out->standard.text_start); -#if !defined(COFF_WITH_pep) && !defined(COFF_WITH_pex64) && !defined(COFF_WITH_peAArch64) +#if !defined(COFF_WITH_pep) && !defined(COFF_WITH_pex64) && !defined(COFF_WITH_peAArch64) && !defined(COFF_WITH_peLoongArch64) /* PE32+ does not have data_start member! */ PUT_AOUTHDR_DATA_START (abfd, aouthdr_in->data_start, aouthdr_out->standard.data_start); @@ -936,9 +938,14 @@ _bfd_XXi_swap_scnhdr_out (bfd * abfd, void * in, void * out) if (scnhdr_int->s_vaddr < pe_data (abfd)->pe_opthdr.ImageBase) _bfd_error_handler (_("%pB:%.8s: section below image base"), abfd, scnhdr_int->s_name); + /* Do not compare lower 32-bits for 64-bit vma. */ +#if !defined(COFF_WITH_pex64) && !defined(COFF_WITH_peAArch64) && !defined(COFF_WITH_peLoongArch64) else if(ss != (ss & 0xffffffff)) _bfd_error_handler (_("%pB:%.8s: RVA truncated"), abfd, scnhdr_int->s_name); PUT_SCNHDR_VADDR (abfd, ss & 0xffffffff, scnhdr_ext->s_vaddr); +#else + PUT_SCNHDR_VADDR (abfd, ss, scnhdr_ext->s_vaddr); +#endif /* NT wants the size data to be rounded up to the next NT_FILE_ALIGNMENT, but zero if it has no content (as in .bss, @@ -1803,7 +1810,7 @@ pe_print_edata (bfd * abfd, void * vfile) static bool pe_print_pdata (bfd * abfd, void * vfile) { -#if defined(COFF_WITH_pep) && !defined(COFF_WITH_pex64) && !defined(COFF_WITH_peAArch64) +#if defined(COFF_WITH_pep) && !defined(COFF_WITH_pex64) && !defined(COFF_WITH_peAArch64) && !defined(COFF_WITH_peLoongArch64) # define PDATA_ROW_SIZE (3 * 8) #else # define PDATA_ROW_SIZE (5 * 4) @@ -1830,7 +1837,7 @@ pe_print_pdata (bfd * abfd, void * vfile) fprintf (file, _("\nThe Function Table (interpreted .pdata section contents)\n")); -#if defined(COFF_WITH_pep) && !defined(COFF_WITH_pex64) && !defined(COFF_WITH_peAArch64) +#if defined(COFF_WITH_pep) && !defined(COFF_WITH_pex64) && !defined(COFF_WITH_peAArch64) && !defined(COFF_WITH_peLoongArch64) fprintf (file, _(" vma:\t\t\tBegin Address End Address Unwind Info\n")); #else @@ -1867,7 +1874,7 @@ pe_print_pdata (bfd * abfd, void * vfile) bfd_vma eh_handler; bfd_vma eh_data; bfd_vma prolog_end_addr; -#if !defined(COFF_WITH_pep) || defined(COFF_WITH_pex64) || defined(COFF_WITH_peAArch64) +#if !defined(COFF_WITH_pep) || defined(COFF_WITH_pex64) || defined(COFF_WITH_peAArch64) || defined(COFF_WITH_peLoongArch64) int em_data; #endif @@ -1885,7 +1892,7 @@ pe_print_pdata (bfd * abfd, void * vfile) /* We are probably into the padding of the section now. */ break; -#if !defined(COFF_WITH_pep) || defined(COFF_WITH_pex64) || defined(COFF_WITH_peAArch64) +#if !defined(COFF_WITH_pep) || defined(COFF_WITH_pex64) || defined(COFF_WITH_peAArch64) || defined(COFF_WITH_peLoongArch64) em_data = ((eh_handler & 0x1) << 2) | (prolog_end_addr & 0x3); #endif eh_handler &= ~(bfd_vma) 0x3; @@ -1896,7 +1903,7 @@ pe_print_pdata (bfd * abfd, void * vfile) bfd_fprintf_vma (abfd, file, begin_addr); fputc (' ', file); bfd_fprintf_vma (abfd, file, end_addr); fputc (' ', file); bfd_fprintf_vma (abfd, file, eh_handler); -#if !defined(COFF_WITH_pep) || defined(COFF_WITH_pex64) || defined(COFF_WITH_peAArch64) +#if !defined(COFF_WITH_pep) || defined(COFF_WITH_pex64) || defined(COFF_WITH_peAArch64) || defined(COFF_WITH_peLoongArch64) fputc (' ', file); bfd_fprintf_vma (abfd, file, eh_data); fputc (' ', file); bfd_fprintf_vma (abfd, file, prolog_end_addr); @@ -2787,7 +2794,7 @@ _bfd_XX_print_private_bfd_data_common (bfd * abfd, void * vfile) bfd_fprintf_vma (abfd, file, i->AddressOfEntryPoint); fprintf (file, "\nBaseOfCode\t\t"); bfd_fprintf_vma (abfd, file, i->BaseOfCode); -#if !defined(COFF_WITH_pep) && !defined(COFF_WITH_pex64) && !defined(COFF_WITH_peAArch64) +#if !defined(COFF_WITH_pep) && !defined(COFF_WITH_pex64) && !defined(COFF_WITH_peAArch64) && !defined(COFF_WITH_peLoongArch64) /* PE32+ does not have BaseOfData member! */ fprintf (file, "\nBaseOfData\t\t"); bfd_fprintf_vma (abfd, file, i->BaseOfData); @@ -3088,7 +3095,7 @@ _bfd_XX_get_symbol_info (bfd * abfd, asymbol *symbol, symbol_info *ret) coff_get_symbol_info (abfd, symbol, ret); } -#if !defined(COFF_WITH_pep) && defined(COFF_WITH_pex64) && defined(COFF_WITH_peAArch64) +#if !defined(COFF_WITH_pep) && (defined(COFF_WITH_pex64) || defined(COFF_WITH_peAArch64) || defined(COFF_WITH_peLoongArch64)) static int sort_x64_pdata (const void *l, const void *r) { @@ -4507,7 +4514,7 @@ _bfd_XXi_final_link_postscript (bfd * abfd, struct coff_final_link_info *pfinfo) the TLS data directory consists of 4 pointers, followed by two 4-byte integer. This implies that the total size is different for 32-bit and 64-bit executables. */ -#if !defined(COFF_WITH_pep) && !defined(COFF_WITH_pex64) && !defined(COFF_WITH_peAArch64) +#if !defined(COFF_WITH_pep) && !defined(COFF_WITH_pex64) && !defined(COFF_WITH_peAArch64) && !defined(COFF_WITH_peLoongArch64) pe_data (abfd)->pe_opthdr.DataDirectory[PE_TLS_TABLE].Size = 0x18; #else pe_data (abfd)->pe_opthdr.DataDirectory[PE_TLS_TABLE].Size = 0x28; @@ -4516,7 +4523,7 @@ _bfd_XXi_final_link_postscript (bfd * abfd, struct coff_final_link_info *pfinfo) /* If there is a .pdata section and we have linked pdata finally, we need to sort the entries ascending. */ -#if !defined(COFF_WITH_pep) && defined(COFF_WITH_pex64) && defined(COFF_WITH_peAArch64) +#if !defined(COFF_WITH_pep) && (defined(COFF_WITH_pex64) || defined(COFF_WITH_peAArch64) || defined(COFF_WITH_peLoongArch64)) { asection *sec = bfd_get_section_by_name (abfd, ".pdata"); diff --git a/bfd/pei-loongarch64.c b/bfd/pei-loongarch64.c new file mode 100644 index 00000000..7221fe66 --- /dev/null +++ b/bfd/pei-loongarch64.c @@ -0,0 +1,75 @@ +/* BFD back-end for LoongArch64 PE IMAGE COFF files. + Copyright (C) 2022 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include "sysdep.h" +#include "bfd.h" + +#define TARGET_SYM loongarch64_pei_vec +#define TARGET_NAME "pei-loongarch64" +#define TARGET_ARCHITECTURE bfd_arch_loongarch +#define TARGET_PAGESIZE 0x4000 +#define TARGET_BIG_ENDIAN 0 +#define TARGET_ARCHIVE 0 +#define TARGET_PRIORITY 0 + +#define COFF_IMAGE_WITH_PE +/* Rename the above into... */ +#define COFF_WITH_peLoongArch64 +#define COFF_WITH_PE +#define PCRELOFFSET true + +/* Long section names not allowed in executable images, only object files. */ +#define COFF_LONG_SECTION_NAMES 0 + +#define COFF_SECTION_ALIGNMENT_ENTRIES \ +{ COFF_SECTION_NAME_EXACT_MATCH (".bss"), \ + COFF_ALIGNMENT_FIELD_EMPTY, COFF_ALIGNMENT_FIELD_EMPTY, 2 }, \ +{ COFF_SECTION_NAME_EXACT_MATCH (".data"), \ + COFF_ALIGNMENT_FIELD_EMPTY, COFF_ALIGNMENT_FIELD_EMPTY, 2 }, \ +{ COFF_SECTION_NAME_EXACT_MATCH (".rdata"), \ + COFF_ALIGNMENT_FIELD_EMPTY, COFF_ALIGNMENT_FIELD_EMPTY, 2 }, \ +{ COFF_SECTION_NAME_EXACT_MATCH (".text"), \ + COFF_ALIGNMENT_FIELD_EMPTY, COFF_ALIGNMENT_FIELD_EMPTY, 2 }, \ +{ COFF_SECTION_NAME_PARTIAL_MATCH (".idata"), \ + COFF_ALIGNMENT_FIELD_EMPTY, COFF_ALIGNMENT_FIELD_EMPTY, 2 }, \ +{ COFF_SECTION_NAME_EXACT_MATCH (".pdata"), \ + COFF_ALIGNMENT_FIELD_EMPTY, COFF_ALIGNMENT_FIELD_EMPTY, 2 }, \ +{ COFF_SECTION_NAME_PARTIAL_MATCH (".debug"), \ + COFF_ALIGNMENT_FIELD_EMPTY, COFF_ALIGNMENT_FIELD_EMPTY, 0 }, \ +{ COFF_SECTION_NAME_PARTIAL_MATCH (".gnu.linkonce.wi."), \ + COFF_ALIGNMENT_FIELD_EMPTY, COFF_ALIGNMENT_FIELD_EMPTY, 0 } + +#define PEI_HEADERS +#include "sysdep.h" +#include "bfd.h" +#include "libbfd.h" +#include "coff/loongarch64.h" +#include "coff/internal.h" +#include "coff/pe.h" +#include "libcoff.h" +#include "libpei.h" +#include "libiberty.h" + +/* Make sure we're setting a 64-bit format. */ +#undef AOUTSZ +#define AOUTSZ PEPAOUTSZ +#define PEAOUTHDR PEPAOUTHDR + +#include "coff-loongarch64.c" diff --git a/bfd/peicode.h b/bfd/peicode.h index 9374e232..800051e7 100644 --- a/bfd/peicode.h +++ b/bfd/peicode.h @@ -231,7 +231,7 @@ coff_swap_scnhdr_in (bfd * abfd, void * ext, void * in) { scnhdr_int->s_vaddr += pe_data (abfd)->pe_opthdr.ImageBase; /* Do not cut upper 32-bits for 64-bit vma. */ -#if !defined(COFF_WITH_pex64) && !defined(COFF_WITH_peAArch64) +#if !defined(COFF_WITH_pex64) && !defined(COFF_WITH_peAArch64) && !defined(COFF_WITH_peLoongArch64) scnhdr_int->s_vaddr &= 0xffffffff; #endif } @@ -763,6 +763,17 @@ static const jump_table jtab[] = 16, 12 }, #endif + +#ifdef LOONGARCH64MAGIC +/* We don't currently support jumping to DLLs, so if + someone does try emit a runtime trap. Through BREAK 0. */ + { LOONGARCH64MAGIC, + { 0x00, 0x00, 0x2a, 0x00 }, + 4, 0 + }, + +#endif + { 0, { 0 }, 0, 0 } }; @@ -920,7 +931,7 @@ pe_ILF_build_a_bfd (bfd * abfd, /* See PR 20907 for a reproducer. */ goto error_return; -#if defined(COFF_WITH_pex64) || defined(COFF_WITH_peAArch64) +#if defined(COFF_WITH_pex64) || defined(COFF_WITH_peAArch64) || defined(COFF_WITH_peLoongArch64) ((unsigned int *) id4->contents)[0] = ordinal; ((unsigned int *) id4->contents)[1] = 0x80000000; ((unsigned int *) id5->contents)[0] = ordinal; @@ -1222,6 +1233,12 @@ pe_ILF_object_p (bfd * abfd) #endif break; + case IMAGE_FILE_MACHINE_LOONGARCH64: +#ifdef LOONGARCH64MAGIC + magic = LOONGARCH64MAGIC; +#endif + break; + case IMAGE_FILE_MACHINE_THUMB: #ifdef THUMBPEMAGIC { diff --git a/bfd/reloc.c b/bfd/reloc.c index 3c768b64..9c58db67 100644 --- a/bfd/reloc.c +++ b/bfd/reloc.c @@ -8339,6 +8339,31 @@ ENUMX ENUMX BFD_RELOC_LARCH_RELAX +ENUMX + BFD_RELOC_LARCH_DELETE + +ENUMX + BFD_RELOC_LARCH_ALIGN + +ENUMX + BFD_RELOC_LARCH_PCREL20_S2 + +ENUMX + BFD_RELOC_LARCH_CFA + +ENUMX + BFD_RELOC_LARCH_ADD6 +ENUMX + BFD_RELOC_LARCH_SUB6 + +ENUMX + BFD_RELOC_LARCH_ADD_ULEB128 +ENUMX + BFD_RELOC_LARCH_SUB_ULEB128 + +ENUMX + BFD_RELOC_LARCH_64_PCREL + ENUMDOC LARCH relocations. diff --git a/bfd/targets.c b/bfd/targets.c index 672dc2bb..d081a310 100644 --- a/bfd/targets.c +++ b/bfd/targets.c @@ -771,6 +771,7 @@ extern const bfd_target lm32_elf32_vec; extern const bfd_target lm32_elf32_fdpic_vec; extern const bfd_target loongarch_elf64_vec; extern const bfd_target loongarch_elf32_vec; +extern const bfd_target loongarch64_pei_vec; extern const bfd_target m32c_elf32_vec; extern const bfd_target m32r_elf32_vec; extern const bfd_target m32r_elf32_le_vec; @@ -1367,6 +1368,7 @@ static const bfd_target * const _bfd_target_vector[] = #ifdef BFD64 &loongarch_elf32_vec, &loongarch_elf64_vec, + &loongarch64_pei_vec, #endif #endif /* not SELECT_VECS */ diff --git a/binutils/readelf.c b/binutils/readelf.c index 90eeb115..407ee42e 100644 --- a/binutils/readelf.c +++ b/binutils/readelf.c @@ -13557,6 +13557,60 @@ target_specific_reloc_handling (Filedata * filedata, switch (filedata->file_header.e_machine) { + case EM_LOONGARCH: + { + switch (reloc_type) + { + /* For .uleb128 .LFE1-.LFB1, loongarch write 0 to object file + at assembly time. */ + case 107: /* R_LARCH_ADD_ULEB128. */ + case 108: /* R_LARCH_SUB_ULEB128. */ + { + uint64_t value = 0; + unsigned int reloc_size = 0; + int leb_ret = 0; + + if (reloc->r_offset < (size_t) (end - start)) + value = read_leb128 (start + reloc->r_offset, end, false, + &reloc_size, &leb_ret); + if (leb_ret != 0 || reloc_size == 0 || reloc_size > 8) + error (_("LoongArch ULEB128 field at 0x%lx contains invalid " + "ULEB128 value\n"), + (long) reloc->r_offset); + + else if (sym_index >= num_syms) + error (_("%s reloc contains invalid symbol index " + "%" PRIu64 "\n"), + (reloc_type == 107 + ? "R_LARCH_ADD_ULEB128" + : "R_LARCH_SUB_ULEB128"), + sym_index); + else + { + if (reloc_type == 107) + value += reloc->r_addend + symtab[sym_index].st_value; + else + value -= reloc->r_addend + symtab[sym_index].st_value; + + /* Write uleb128 value to p. */ + bfd_byte *p = start + reloc->r_offset; + do + { + bfd_byte c = value & 0x7f; + value >>= 7; + if (--reloc_size != 0) + c |= 0x80; + *p++ = c; + } + while (reloc_size); + } + + return true; + } + } + break; + } + case EM_MSP430: case EM_MSP430_OLD: { @@ -14282,6 +14336,8 @@ is_32bit_inplace_add_reloc (Filedata * filedata, unsigned int reloc_type) /* Please keep this table alpha-sorted for ease of visual lookup. */ switch (filedata->file_header.e_machine) { + case EM_LOONGARCH: + return reloc_type == 50; /* R_LARCH_ADD32. */ case EM_RISCV: return reloc_type == 35; /* R_RISCV_ADD32. */ default: @@ -14298,6 +14354,8 @@ is_32bit_inplace_sub_reloc (Filedata * filedata, unsigned int reloc_type) /* Please keep this table alpha-sorted for ease of visual lookup. */ switch (filedata->file_header.e_machine) { + case EM_LOONGARCH: + return reloc_type == 55; /* R_LARCH_SUB32. */ case EM_RISCV: return reloc_type == 39; /* R_RISCV_SUB32. */ default: @@ -14314,6 +14372,8 @@ is_64bit_inplace_add_reloc (Filedata * filedata, unsigned int reloc_type) /* Please keep this table alpha-sorted for ease of visual lookup. */ switch (filedata->file_header.e_machine) { + case EM_LOONGARCH: + return reloc_type == 51; /* R_LARCH_ADD64. */ case EM_RISCV: return reloc_type == 36; /* R_RISCV_ADD64. */ default: @@ -14330,6 +14390,8 @@ is_64bit_inplace_sub_reloc (Filedata * filedata, unsigned int reloc_type) /* Please keep this table alpha-sorted for ease of visual lookup. */ switch (filedata->file_header.e_machine) { + case EM_LOONGARCH: + return reloc_type == 56; /* R_LARCH_SUB64. */ case EM_RISCV: return reloc_type == 40; /* R_RISCV_SUB64. */ default: @@ -14346,6 +14408,8 @@ is_16bit_inplace_add_reloc (Filedata * filedata, unsigned int reloc_type) /* Please keep this table alpha-sorted for ease of visual lookup. */ switch (filedata->file_header.e_machine) { + case EM_LOONGARCH: + return reloc_type == 48; /* R_LARCH_ADD16. */ case EM_RISCV: return reloc_type == 34; /* R_RISCV_ADD16. */ default: @@ -14362,6 +14426,8 @@ is_16bit_inplace_sub_reloc (Filedata * filedata, unsigned int reloc_type) /* Please keep this table alpha-sorted for ease of visual lookup. */ switch (filedata->file_header.e_machine) { + case EM_LOONGARCH: + return reloc_type == 53; /* R_LARCH_SUB16. */ case EM_RISCV: return reloc_type == 38; /* R_RISCV_SUB16. */ default: @@ -14378,6 +14444,8 @@ is_8bit_inplace_add_reloc (Filedata * filedata, unsigned int reloc_type) /* Please keep this table alpha-sorted for ease of visual lookup. */ switch (filedata->file_header.e_machine) { + case EM_LOONGARCH: + return reloc_type == 47; /* R_LARCH_ADD8. */ case EM_RISCV: return reloc_type == 33; /* R_RISCV_ADD8. */ default: @@ -14394,6 +14462,8 @@ is_8bit_inplace_sub_reloc (Filedata * filedata, unsigned int reloc_type) /* Please keep this table alpha-sorted for ease of visual lookup. */ switch (filedata->file_header.e_machine) { + case EM_LOONGARCH: + return reloc_type == 52; /* R_LARCH_SUB8. */ case EM_RISCV: return reloc_type == 37; /* R_RISCV_SUB8. */ default: @@ -14401,6 +14471,21 @@ is_8bit_inplace_sub_reloc (Filedata * filedata, unsigned int reloc_type) } } +/* Like is_32bit_abs_reloc except that it returns TRUE iff RELOC_TYPE is + a 6-bit inplace add RELA relocation used in DWARF debug sections. */ + +static bool +is_6bit_inplace_add_reloc (Filedata * filedata, unsigned int reloc_type) +{ + switch (filedata->file_header.e_machine) + { + case EM_LOONGARCH: + return reloc_type == 105; /* R_LARCH_ADD6. */ + default: + return false; + } +} + /* Like is_32bit_abs_reloc except that it returns TRUE iff RELOC_TYPE is a 6-bit inplace sub RELA relocation used in DWARF debug sections. */ @@ -14409,6 +14494,8 @@ is_6bit_inplace_sub_reloc (Filedata * filedata, unsigned int reloc_type) { switch (filedata->file_header.e_machine) { + case EM_LOONGARCH: + return reloc_type == 106; /* R_LARCH_SUB6. */ case EM_RISCV: return reloc_type == 52; /* R_RISCV_SUB6. */ default: @@ -14658,7 +14745,8 @@ apply_relocations (Filedata * filedata, reloc_inplace = true; } else if ((reloc_subtract = is_6bit_inplace_sub_reloc (filedata, - reloc_type))) + reloc_type)) + || is_6bit_inplace_add_reloc (filedata, reloc_type)) { reloc_size = 1; reloc_inplace = true; @@ -14748,7 +14836,8 @@ apply_relocations (Filedata * filedata, reloc_size); } else if (is_6bit_abs_reloc (filedata, reloc_type) - || is_6bit_inplace_sub_reloc (filedata, reloc_type)) + || is_6bit_inplace_sub_reloc (filedata, reloc_type) + || is_6bit_inplace_add_reloc (filedata, reloc_type)) { if (reloc_subtract) addend -= sym->st_value; diff --git a/binutils/testsuite/binutils-all/loongarch64/loongarch64.exp b/binutils/testsuite/binutils-all/loongarch64/loongarch64.exp new file mode 100644 index 00000000..bd1d5eba --- /dev/null +++ b/binutils/testsuite/binutils-all/loongarch64/loongarch64.exp @@ -0,0 +1,30 @@ +# Copyright (C) 2022 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +if {![istarget "loongarch64*-*-*"] + || ![is_elf_format]} then { + return +} + +set tempfile tmpdir/loongarch64temp.o +set copyfile tmpdir/loongarch64copy + +set test_list [lsort [glob -nocomplain $srcdir/$subdir/*.d]] +foreach t $test_list { + # We need to strip the ".d", but can leave the dirname. + verbose [file rootname $t] + run_dump_test [file rootname $t] +} diff --git a/binutils/testsuite/binutils-all/loongarch64/pei-loongarch64.d b/binutils/testsuite/binutils-all/loongarch64/pei-loongarch64.d new file mode 100644 index 00000000..574b3e54 --- /dev/null +++ b/binutils/testsuite/binutils-all/loongarch64/pei-loongarch64.d @@ -0,0 +1,15 @@ +#ld: -e0 +#PROG: objcopy +#objcopy: -j .text -j .sdata -j .data -j .dynamic -j .dynsym -j .rel -j .rela -j .rel.* -j .rela.* -j .rel* -j .rela* -j .reloc --target=pei-loongarch64 +#objdump: -h -f +#name: Check if efi app format is recognized + +.*: file format pei-loongarch64 +architecture: Loongarch64, flags 0x00000132: +EXEC_P, HAS_SYMS, HAS_LOCALS, D_PAGED +start address 0x0000000000000000 + +Sections: +Idx Name Size VMA LMA File off Algn + 0 \.text 0000003c 0[^ ]+ 0[^ ]+ 0[^ ]+ 2\*\*2 + CONTENTS, ALLOC, LOAD, READONLY, CODE diff --git a/binutils/testsuite/binutils-all/loongarch64/pei-loongarch64.s b/binutils/testsuite/binutils-all/loongarch64/pei-loongarch64.s new file mode 100644 index 00000000..1e6710ac --- /dev/null +++ b/binutils/testsuite/binutils-all/loongarch64/pei-loongarch64.s @@ -0,0 +1,33 @@ + .file "test_pei.c" + .text + .align 2 + .globl main + .type main, @function +main: +.LFB0 = . + .cfi_startproc + addi.d $r3,$r3,-32 + .cfi_def_cfa_offset 32 + st.d $r22,$r3,24 + .cfi_offset 22, -8 + addi.d $r22,$r3,32 + .cfi_def_cfa 22, 0 + addi.w $r12,$r0,1 # 0x1 + st.w $r12,$r22,-20 + addi.w $r12,$r0,2 # 0x2 + st.w $r12,$r22,-24 + ld.w $r13,$r22,-20 + ld.w $r12,$r22,-24 + mul.w $r12,$r13,$r12 + slli.w $r12,$r12,0 + or $r4,$r12,$r0 + ld.d $r22,$r3,24 + .cfi_restore 22 + addi.d $r3,$r3,32 + .cfi_def_cfa_register 3 + jr $r1 + .cfi_endproc +.LFE0: + .size main, .-main + .ident "GCC: (GNU) 12.1.0" + .section .note.GNU-stack,"",@progbits diff --git a/binutils/testsuite/binutils-all/readelf.exp b/binutils/testsuite/binutils-all/readelf.exp index cf5fb64d..200efdfb 100644 --- a/binutils/testsuite/binutils-all/readelf.exp +++ b/binutils/testsuite/binutils-all/readelf.exp @@ -488,17 +488,24 @@ if {![binutils_assemble $srcdir/$subdir/z.s tmpdir/z.o]} then { readelf_test {--decompress --hex-dump .debug_loc} $tempfile readelf.z } +set flags "" + # Skip the next test for the RISCV architectures because they # do not support .ULEB128 pseudo-ops with non-constant values. if ![istarget "riscv*-*-*"] then { set hpux "" if [istarget "hppa*64*-*-hpux*"] { - set hpux "--defsym HPUX=1" + set flags "--defsym HPUX=1" } + # LoongArch relax align add nops, so label subtractions will increase + if [istarget "loongarch*-*-*"] { + set flags "-mno-relax" + } + # Assemble the DWARF-5 test file. - if {![binutils_assemble_flags $srcdir/$subdir/dw5.S tmpdir/dw5.o $hpux]} then { + if {![binutils_assemble_flags $srcdir/$subdir/dw5.S tmpdir/dw5.o $flags]} then { unsupported "readelf -wiaoRlL dw5 (failed to assemble)" } else { diff --git a/gas/config/loongarch-lex-wrapper.c b/gas/config/loongarch-lex-wrapper.c index 3bb0b14c..4ddeeb73 100644 --- a/gas/config/loongarch-lex-wrapper.c +++ b/gas/config/loongarch-lex-wrapper.c @@ -16,5 +16,5 @@ along with this program; see the file COPYING3. If not, see <http://www.gnu.org/licenses/>. */ -#include "sysdep.h" +#include "config.h" #include "config/loongarch-lex.c" diff --git a/gas/config/loongarch-parse.y b/gas/config/loongarch-parse.y index 902d7204..87046877 100644 --- a/gas/config/loongarch-parse.y +++ b/gas/config/loongarch-parse.y @@ -100,6 +100,25 @@ my_getExpression (expressionS *ep, const char *str) return ret; } +static void +emit_const_var (const char *op) +{ + expressionS ep; + + if (end <= top) + as_fatal (_("expr too huge")); + + my_getExpression (&ep, op); + + if (ep.X_op != O_constant) + as_bad ("illegal operand: %s", op); + + top->value.X_op = O_constant; + top->value.X_add_number = ep.X_add_number; + top->type = BFD_RELOC_LARCH_SOP_PUSH_ABSOLUTE; + top++; +} + static void reloc (const char *op_c_str, const char *id_c_str, offsetT addend) { @@ -318,6 +337,7 @@ offsetT imm; primary_expression : INTEGER {emit_const ($1);} + | IDENTIFIER {emit_const_var ($1);} | '(' expression ')' | '%' IDENTIFIER '(' IDENTIFIER addend ')' {reloc ($2, $4, $5); free ($2); free ($4);} | '%' IDENTIFIER '(' INTEGER addend ')' {reloc ($2, NULL, $4 + $5); free ($2);} diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c index 93412b69..b776a9ac 100644 --- a/gas/config/tc-loongarch.c +++ b/gas/config/tc-loongarch.c @@ -20,6 +20,7 @@ see <http://www.gnu.org/licenses/>. */ #include "as.h" +#include "subsegs.h" #include "dw2gencfi.h" #include "loongarch-lex.h" #include "elf/loongarch.h" @@ -70,6 +71,7 @@ struct loongarch_cl_insn long where; /* The relocs associated with the instruction, if any. */ fixS *fixp[MAX_RELOC_NUMBER_A_INSN]; + long macro_id; }; #ifndef DEFAULT_ARCH @@ -116,6 +118,8 @@ enum options OPTION_LA_LOCAL_WITH_ABS, OPTION_LA_GLOBAL_WITH_PCREL, OPTION_LA_GLOBAL_WITH_ABS, + OPTION_RELAX, + OPTION_NO_RELAX, OPTION_END_OF_ENUM, }; @@ -130,6 +134,9 @@ struct option md_longopts[] = { "mla-global-with-pcrel", no_argument, NULL, OPTION_LA_GLOBAL_WITH_PCREL }, { "mla-global-with-abs", no_argument, NULL, OPTION_LA_GLOBAL_WITH_ABS }, + { "mrelax", no_argument, NULL, OPTION_RELAX }, + { "mno-relax", no_argument, NULL, OPTION_NO_RELAX }, + { NULL, no_argument, NULL, 0 } }; @@ -158,6 +165,10 @@ md_parse_option (int c, const char *arg) { LARCH_opts.ase_ilp32 = 1; LARCH_opts.ase_lp64 = 1; + LARCH_opts.ase_lsx = 1; + LARCH_opts.ase_lasx = 1; + LARCH_opts.ase_lvz = 1; + LARCH_opts.ase_lbt = 1; LARCH_opts.ase_abi = lp64[suf[4]]; } else if (strncasecmp (arg, "ilp32", 5) == 0 && ilp32[suf[5]] != 0) @@ -195,6 +206,14 @@ md_parse_option (int c, const char *arg) LARCH_opts.ase_gabs = 1; break; + case OPTION_RELAX: + LARCH_opts.relax = 1; + break; + + case OPTION_NO_RELAX: + LARCH_opts.relax = 0; + break; + case OPTION_IGNORE: break; @@ -205,8 +224,14 @@ md_parse_option (int c, const char *arg) return ret; } +static const char *const *r_abi_names = NULL; +static const char *const *f_abi_names = NULL; static struct htab *r_htab = NULL; +static struct htab *r_deprecated_htab = NULL; static struct htab *f_htab = NULL; +static struct htab *f_deprecated_htab = NULL; +static struct htab *fc_htab = NULL; +static struct htab *fcn_htab = NULL; static struct htab *c_htab = NULL; static struct htab *cr_htab = NULL; static struct htab *v_htab = NULL; @@ -223,6 +248,10 @@ loongarch_after_parse_args () LARCH_opts.ase_abi = EF_LOONGARCH_ABI_DOUBLE_FLOAT; LARCH_opts.ase_ilp32 = 1; LARCH_opts.ase_lp64 = 1; + LARCH_opts.ase_lsx = 1; + LARCH_opts.ase_lasx = 1; + LARCH_opts.ase_lvz = 1; + LARCH_opts.ase_lbt = 1; } else if (strcmp (default_arch, "loongarch32") == 0) { @@ -250,7 +279,11 @@ loongarch_after_parse_args () /* Init ilp32/lp64 registers names. */ if (!r_htab) r_htab = str_htab_create (), str_hash_insert (r_htab, "", 0, 0); + if (!r_deprecated_htab) + r_deprecated_htab = str_htab_create (), + str_hash_insert (r_deprecated_htab, "", 0, 0); + r_abi_names = loongarch_r_normal_name; for (i = 0; i < ARRAY_SIZE (loongarch_r_normal_name); i++) str_hash_insert (r_htab, loongarch_r_normal_name[i], (void *) (i + 1), 0); @@ -265,11 +298,29 @@ loongarch_after_parse_args () { if (!f_htab) f_htab = str_htab_create (), str_hash_insert (f_htab, "", 0, 0); + if (!f_deprecated_htab) + f_deprecated_htab = str_htab_create (), + str_hash_insert (f_deprecated_htab, "", 0, 0); + f_abi_names = loongarch_f_normal_name; for (i = 0; i < ARRAY_SIZE (loongarch_f_normal_name); i++) str_hash_insert (f_htab, loongarch_f_normal_name[i], (void *) (i + 1), 0); + if (!fc_htab) + fc_htab = str_htab_create (), str_hash_insert (fc_htab, "", 0, 0); + + for (i = 0; i < ARRAY_SIZE (loongarch_fc_normal_name); i++) + str_hash_insert (fc_htab, loongarch_fc_normal_name[i], (void *) (i + 1), + 0); + + if (!fcn_htab) + fcn_htab = str_htab_create (), str_hash_insert (fcn_htab, "", 0, 0); + + for (i = 0; i < ARRAY_SIZE (loongarch_fc_numeric_name); i++) + str_hash_insert (fcn_htab, loongarch_fc_numeric_name[i], (void *) (i + 1), + 0); + if (!c_htab) c_htab = str_htab_create (), str_hash_insert (c_htab, "", 0, 0); @@ -302,22 +353,24 @@ loongarch_after_parse_args () /* Init lp64 registers alias. */ if (LARCH_opts.ase_lp64) { + r_abi_names = loongarch_r_lp64_name; for (i = 0; i < ARRAY_SIZE (loongarch_r_lp64_name); i++) str_hash_insert (r_htab, loongarch_r_lp64_name[i], (void *) (i + 1), 0); - for (i = 0; i < ARRAY_SIZE (loongarch_r_lp64_name1); i++) - str_hash_insert (r_htab, loongarch_r_lp64_name1[i], (void *) (i + 1), - 0); + for (i = 0; i < ARRAY_SIZE (loongarch_r_lp64_name_deprecated); i++) + str_hash_insert (r_deprecated_htab, loongarch_r_lp64_name_deprecated[i], + (void *) (i + 1), 0); } /* Init float-lp64 registers alias */ if ((LARCH_opts.ase_sf || LARCH_opts.ase_df) && LARCH_opts.ase_lp64) { + f_abi_names = loongarch_f_lp64_name; for (i = 0; i < ARRAY_SIZE (loongarch_f_lp64_name); i++) str_hash_insert (f_htab, loongarch_f_lp64_name[i], (void *) (i + 1), 0); - for (i = 0; i < ARRAY_SIZE (loongarch_f_lp64_name1); i++) - str_hash_insert (f_htab, loongarch_f_lp64_name1[i], + for (i = 0; i < ARRAY_SIZE (loongarch_f_lp64_name_deprecated); i++) + str_hash_insert (f_deprecated_htab, loongarch_f_lp64_name_deprecated[i], (void *) (i + 1), 0); } } @@ -460,7 +513,6 @@ get_internal_label (expressionS *label_expr, unsigned long label, int augend /* 0 for previous, 1 for next. */) { assert (label < INTERNAL_LABEL_SPECIAL); - if (augend == 0 && internal_label_count[label] == 0) as_fatal (_("internal error: we have no internal label yet")); label_expr->X_op = O_symbol; label_expr->X_add_symbol = @@ -582,24 +634,6 @@ loongarch_args_parser_can_match_arg_helper (char esc_ch1, char esc_ch2, if (!ip->match_now) break; - if (esc_ch1 == 's') - switch (esc_ch2) - { - case 'c': - ip->match_now = reloc_num == 0; - break; - } - else - switch (esc_ch2) - { - case 'c': - ip->match_now = reloc_num == 0 && 0 <= imm; - break; - } - - if (!ip->match_now) - break; - ret = imm; if (reloc_num) { @@ -635,13 +669,26 @@ loongarch_args_parser_can_match_arg_helper (char esc_ch1, char esc_ch2, as_fatal ( _("not support reloc bit-field\nfmt: %c%c %s\nargs: %s"), esc_ch1, esc_ch2, bit_field, arg); + if (ip->reloc_info[0].type >= BFD_RELOC_LARCH_B16 - && ip->reloc_info[0].type < BFD_RELOC_LARCH_RELAX) + && ip->reloc_info[0].type < BFD_RELOC_LARCH_64_PCREL) { /* As we compact stack-relocs, it is no need for pop operation. But break out until here in order to check the imm field. May be reloc_num > 1 if implement relax? */ ip->reloc_num += reloc_num; + reloc_type = ip->reloc_info[0].type; + + if (LARCH_opts.relax && ip->macro_id + && (BFD_RELOC_LARCH_PCALA_HI20 == reloc_type + || BFD_RELOC_LARCH_PCALA_LO12 == reloc_type + || BFD_RELOC_LARCH_GOT_PC_HI20 == reloc_type + || BFD_RELOC_LARCH_GOT_PC_LO12 == reloc_type)) + { + ip->reloc_info[ip->reloc_num].type = BFD_RELOC_LARCH_RELAX; + ip->reloc_info[ip->reloc_num].value = const_0; + ip->reloc_num++; + } break; } reloc_num++; @@ -654,11 +701,40 @@ loongarch_args_parser_can_match_arg_helper (char esc_ch1, char esc_ch2, imm = (intptr_t) str_hash_find (r_htab, arg); ip->match_now = 0 < imm; ret = imm - 1; + if (ip->match_now) + break; + /* Handle potential usage of deprecated register aliases. */ + imm = (intptr_t) str_hash_find (r_deprecated_htab, arg); + ip->match_now = 0 < imm; + ret = imm - 1; + if (ip->match_now && !ip->macro_id) + as_warn (_("register alias %s is deprecated, use %s instead"), + arg, r_abi_names[ret]); break; case 'f': - imm = (intptr_t) str_hash_find (f_htab, arg); + switch (esc_ch2) + { + case 'c': + imm = (intptr_t) str_hash_find (fc_htab, arg); + if (0 >= imm) + { + imm = (intptr_t) str_hash_find (fcn_htab, arg); + } + break; + default: + imm = (intptr_t) str_hash_find (f_htab, arg); + } + ip->match_now = 0 < imm; + ret = imm - 1; + if (ip->match_now && !ip->macro_id) + break; + /* Handle potential usage of deprecated register aliases. */ + imm = (intptr_t) str_hash_find (f_deprecated_htab, arg); ip->match_now = 0 < imm; ret = imm - 1; + if (ip->match_now) + as_warn (_("register alias %s is deprecated, use %s instead"), + arg, f_abi_names[ret]); break; case 'c': switch (esc_ch2) @@ -761,7 +837,8 @@ get_loongarch_opcode (struct loongarch_cl_insn *insn) for (it = ase->opcodes; it->name; it++) { if ((!it->include || (it->include && *it->include)) - && (!it->exclude || (it->exclude && !(*it->exclude)))) + && (!it->exclude || (it->exclude && !(*it->exclude))) + && !(it->pinfo & INSN_DIS_ALIAS)) str_hash_insert (ase->name_hash_entry, it->name, (void *) it, 0); } @@ -853,8 +930,11 @@ move_insn (struct loongarch_cl_insn *insn, fragS *frag, long where) insn->where = where; for (i = 0; i < insn->reloc_num; i++) { - insn->fixp[i]->fx_frag = frag; - insn->fixp[i]->fx_where = where; + if (insn->fixp[i]) + { + insn->fixp[i]->fx_frag = frag; + insn->fixp[i]->fx_where = where; + } } install_insn (insn); } @@ -893,6 +973,22 @@ append_fixp_and_insn (struct loongarch_cl_insn *ip) as_fatal (_("Internal error: not support relax now")); else append_fixed_insn (ip); + + /* We need to start a new frag after any instruction that can be + optimized away or compressed by the linker during relaxation, to prevent + the assembler from computing static offsets across such an instruction. + + This is necessary to get correct .eh_frame cfa info. If one cfa's two + symbol is not in the same frag, it will generate relocs to calculate + symbol subtraction. (gas/dw2gencfi.c:output_cfi_insn: + if (symbol_get_frag (to) == symbol_get_frag (from))) */ + if (LARCH_opts.relax + && (BFD_RELOC_LARCH_PCALA_HI20 == reloc_info[0].type + || BFD_RELOC_LARCH_GOT_PC_HI20 == reloc_info[0].type)) + { + frag_wane (frag_now); + frag_new (0); + } } /* Ask helper for returning a malloced c_str or NULL. */ @@ -986,7 +1082,7 @@ assember_macro_helper (const char *const args[], void *context_ptr) * assuming 'not starting with space and not ending with space' or pass in * empty c_str. */ static void -loongarch_assemble_INSNs (char *str) +loongarch_assemble_INSNs (char *str, struct loongarch_cl_insn *ctx) { char *rest; size_t len_str = strlen(str); @@ -1009,6 +1105,7 @@ loongarch_assemble_INSNs (char *str) struct loongarch_cl_insn the_one = { 0 }; the_one.name = str; + the_one.macro_id = ctx->macro_id; for (; *str && *str != ' '; str++) ; @@ -1032,24 +1129,27 @@ loongarch_assemble_INSNs (char *str) append_fixp_and_insn (&the_one); if (the_one.insn_length == 0 && the_one.insn->macro) { + the_one.macro_id = 1; + char *c_str = loongarch_expand_macro (the_one.insn->macro, the_one.arg_strs, assember_macro_helper, &the_one, len_str); - loongarch_assemble_INSNs (c_str); + loongarch_assemble_INSNs (c_str, &the_one); free (c_str); } } while (0); if (*rest != '\0') - loongarch_assemble_INSNs (rest); + loongarch_assemble_INSNs (rest, ctx); } void md_assemble (char *str) { - loongarch_assemble_INSNs (str); + struct loongarch_cl_insn the_one = { 0 }; + loongarch_assemble_INSNs (str, &the_one); } const char * @@ -1080,7 +1180,7 @@ static void fix_reloc_insn (fixS *fixP, bfd_vma reloc_val, char *buf) insn = bfd_getl32 (buf); - if (!loongarch_adjust_reloc_bitsfield(howto, &reloc_val)) + if (!loongarch_adjust_reloc_bitsfield (NULL, howto, &reloc_val)) as_warn_where (fixP->fx_file, fixP->fx_line, "Reloc overflow"); insn = (insn & (insn_t)howto->src_mask) @@ -1095,7 +1195,6 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) static int64_t stack_top; static int last_reloc_is_sop_push_pcrel_1 = 0; int last_reloc_is_sop_push_pcrel = last_reloc_is_sop_push_pcrel_1; - segT sub_segment; last_reloc_is_sop_push_pcrel_1 = 0; char *buf = fixP->fx_frag->fr_literal + fixP->fx_where; @@ -1155,22 +1254,43 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) fix_reloc_insn (fixP, (bfd_vma)stack_top, buf); break; + /* LARCH only has R_LARCH_64/32, not has R_LARCH_24/16/8. + For BFD_RELOC_64/32, if fx_addsy and fx_subsy not null, wer need + generate BFD_RELOC_LARCH_ADD64/32 and BFD_RELOC_LARCH_SUB64/32 here. + Then will parse howto table bfd_reloc_code_real_type to generate + R_LARCH_ADD64/32 and R_LARCH_SUB64/32 reloc at tc_gen_reloc function. + If only fx_addsy not null, skip here directly, then generate + R_LARCH_64/32. + + For BFD_RELOC_24/16/8, if fx_addsy and fx_subsy not null, wer need + generate BFD_RELOC_LARCH_ADD24/16/8 and BFD_RELOC_LARCH_SUB24/16/8 here. + Then will parse howto table bfd_reloc_code_real_type to generate + R_LARCH_ADD24/16/8 and R_LARCH_SUB24/16/8 reloc at tc_gen_reloc + function. If only fx_addsy not null, we generate + BFD_RELOC_LARCH_ADD24/16/8 only, then generate R_LARCH_24/16/8. + To avoid R_LARCH_ADDxx add extra value, we write 0 first + (use md_number_to_chars (buf, 0, fixP->fx_size)). + */ + case BFD_RELOC_64: case BFD_RELOC_32: - if (fixP->fx_r_type == BFD_RELOC_32 - && fixP->fx_addsy && fixP->fx_subsy - && (sub_segment = S_GET_SEGMENT (fixP->fx_subsy)) - && strcmp (sub_segment->name, ".eh_frame") == 0 - && S_GET_VALUE (fixP->fx_subsy) - == fixP->fx_frag->fr_address + fixP->fx_where) + if (fixP->fx_pcrel) { - fixP->fx_r_type = BFD_RELOC_LARCH_32_PCREL; - fixP->fx_subsy = NULL; - break; + switch (fixP->fx_r_type) + { + case BFD_RELOC_64: + fixP->fx_r_type = BFD_RELOC_LARCH_64_PCREL; + break; + case BFD_RELOC_32: + fixP->fx_r_type = BFD_RELOC_LARCH_32_PCREL; + break; + default: + break; + } } - if (fixP->fx_subsy) + if (fixP->fx_addsy && fixP->fx_subsy) { fixP->fx_next = xmemdup (fixP, sizeof (*fixP), sizeof (*fixP)); fixP->fx_next->fx_addsy = fixP->fx_subsy; @@ -1204,34 +1324,37 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) case BFD_RELOC_24: case BFD_RELOC_16: case BFD_RELOC_8: - fixP->fx_next = xmemdup (fixP, sizeof (*fixP), sizeof (*fixP)); - fixP->fx_next->fx_addsy = fixP->fx_subsy; - fixP->fx_next->fx_subsy = NULL; - fixP->fx_next->fx_offset = 0; - fixP->fx_subsy = NULL; - - switch (fixP->fx_r_type) + if (fixP->fx_addsy) { - case BFD_RELOC_24: - fixP->fx_r_type = BFD_RELOC_LARCH_ADD24; - fixP->fx_next->fx_r_type = BFD_RELOC_LARCH_SUB24; - break; - case BFD_RELOC_16: - fixP->fx_r_type = BFD_RELOC_LARCH_ADD16; - fixP->fx_next->fx_r_type = BFD_RELOC_LARCH_SUB16; - break; - case BFD_RELOC_8: - fixP->fx_r_type = BFD_RELOC_LARCH_ADD8; - fixP->fx_next->fx_r_type = BFD_RELOC_LARCH_SUB8; - break; - default: - break; - } + fixP->fx_next = xmemdup (fixP, sizeof (*fixP), sizeof (*fixP)); + fixP->fx_next->fx_addsy = fixP->fx_subsy; + fixP->fx_next->fx_subsy = NULL; + fixP->fx_next->fx_offset = 0; + fixP->fx_subsy = NULL; - md_number_to_chars (buf, 0, fixP->fx_size); + switch (fixP->fx_r_type) + { + case BFD_RELOC_24: + fixP->fx_r_type = BFD_RELOC_LARCH_ADD24; + fixP->fx_next->fx_r_type = BFD_RELOC_LARCH_SUB24; + break; + case BFD_RELOC_16: + fixP->fx_r_type = BFD_RELOC_LARCH_ADD16; + fixP->fx_next->fx_r_type = BFD_RELOC_LARCH_SUB16; + break; + case BFD_RELOC_8: + fixP->fx_r_type = BFD_RELOC_LARCH_ADD8; + fixP->fx_next->fx_r_type = BFD_RELOC_LARCH_SUB8; + break; + default: + break; + } - if (fixP->fx_next->fx_addsy == NULL) - fixP->fx_next->fx_done = 1; + md_number_to_chars (buf, 0, fixP->fx_size); + + if (fixP->fx_next->fx_addsy == NULL) + fixP->fx_next->fx_done = 1; + } if (fixP->fx_addsy == NULL) { @@ -1240,6 +1363,67 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) } break; + case BFD_RELOC_LARCH_CFA: + if (fixP->fx_addsy && fixP->fx_subsy) + { + fixP->fx_next = xmemdup (fixP, sizeof (*fixP), sizeof (*fixP)); + fixP->fx_next->fx_addsy = fixP->fx_subsy; + fixP->fx_next->fx_subsy = NULL; + fixP->fx_next->fx_offset = 0; + fixP->fx_subsy = NULL; + + unsigned int subtype; + offsetT loc; + subtype = bfd_get_8 (NULL, &((fragS *) + (fixP->fx_frag->fr_opcode))->fr_literal[fixP->fx_where]); + loc = fixP->fx_frag->fr_fix - (subtype & 7); + switch (subtype) + { + case DW_CFA_advance_loc1: + fixP->fx_where = loc + 1; + fixP->fx_next->fx_where = loc + 1; + fixP->fx_r_type = BFD_RELOC_LARCH_ADD8; + fixP->fx_next->fx_r_type = BFD_RELOC_LARCH_SUB8; + md_number_to_chars (buf+1, 0, fixP->fx_size); + break; + + case DW_CFA_advance_loc2: + fixP->fx_size = 2; + fixP->fx_next->fx_size = 2; + fixP->fx_where = loc + 1; + fixP->fx_next->fx_where = loc + 1; + fixP->fx_r_type = BFD_RELOC_LARCH_ADD16; + fixP->fx_next->fx_r_type = BFD_RELOC_LARCH_SUB16; + md_number_to_chars (buf+1, 0, fixP->fx_size); + break; + + case DW_CFA_advance_loc4: + fixP->fx_size = 4; + fixP->fx_next->fx_size = 4; + fixP->fx_where = loc; + fixP->fx_next->fx_where = loc; + fixP->fx_r_type = BFD_RELOC_LARCH_ADD32; + fixP->fx_next->fx_r_type = BFD_RELOC_LARCH_SUB32; + md_number_to_chars (buf+1, 0, fixP->fx_size); + break; + + default: + if (subtype < 0x80 && (subtype & 0x40)) + { + /* DW_CFA_advance_loc. */ + fixP->fx_frag = (fragS *) fixP->fx_frag->fr_opcode; + fixP->fx_next->fx_frag = fixP->fx_frag; + fixP->fx_r_type = BFD_RELOC_LARCH_ADD6; + fixP->fx_next->fx_r_type = BFD_RELOC_LARCH_SUB6; + md_number_to_chars (buf, 0x40, fixP->fx_size); + } + else + as_fatal (_("internal: bad CFA value #%d"), subtype); + break; + } + } + break; + case BFD_RELOC_LARCH_B16: case BFD_RELOC_LARCH_B21: case BFD_RELOC_LARCH_B26: @@ -1254,11 +1438,28 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) int64_t sym_addend = S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset; int64_t pc = fixP->fx_where + fixP->fx_frag->fr_address; fix_reloc_insn (fixP, sym_addend - pc, buf); - fixP->fx_done = 1; - } + /* If relax, symbol value may change at link time, so reloc need to + be saved. */ + if (!LARCH_opts.relax) + fixP->fx_done = 1; + } break; + /* Because ADD_ULEB128/SUB_ULEB128 always occur in pairs. + So just deal with one is ok. + case BFD_RELOC_LARCH_ADD_ULEB128: */ + case BFD_RELOC_LARCH_SUB_ULEB128: + { + unsigned int len = 0; + len = loongarch_get_uleb128_length ((bfd_byte *)buf); + bfd_byte *endp = (bfd_byte*) buf + len -1; + /* Clean the uleb128 value to 0. Do not reduce the length. */ + memset (buf, 0x80, len - 1); + *endp = 0; + break; + } + default: break; } @@ -1276,19 +1477,7 @@ int md_estimate_size_before_relax (fragS *fragp ATTRIBUTE_UNUSED, asection *segtype ATTRIBUTE_UNUSED) { - return 0; -} - -int -loongarch_fix_adjustable (fixS *fix) -{ - /* Prevent all adjustments to global symbols. */ - if (S_IS_EXTERNAL (fix->fx_addsy) - || S_IS_WEAK (fix->fx_addsy) - || S_FORCE_RELOC (fix->fx_addsy, true)) - return 0; - - return 1; + return (fragp->fr_var = 4); } /* Translate internal representation of relocation info to BFD target @@ -1318,9 +1507,25 @@ tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) /* Convert a machine dependent frag. */ void md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec ATTRIBUTE_UNUSED, - fragS *fragp ATTRIBUTE_UNUSED) + fragS *fragp) { - /* fragp->fr_fix += 8; */ + expressionS exp; + exp.X_op = O_symbol; + exp.X_add_symbol = fragp->fr_symbol; + exp.X_add_number = fragp->fr_offset; + bfd_byte *buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix; + + fixS *fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, + 4, &exp, false, fragp->fr_subtype); + buf += 4; + + fixp->fx_file = fragp->fr_file; + fixp->fx_line = fragp->fr_line; + fragp->fr_fix += fragp->fr_var; + + gas_assert (fragp->fr_next == NULL + || (fragp->fr_next->fr_address - fragp->fr_address + == fragp->fr_fix)); } /* Standard calling conventions leave the CFA at SP on entry. */ @@ -1330,6 +1535,51 @@ loongarch_cfi_frame_initial_instructions (void) cfi_add_CFA_def_cfa_register (3 /* $sp */); } +void +loongarch_pre_output_hook (void) +{ + const frchainS *frch; + segT s; + + if (!LARCH_opts.relax) + return; + + /* Save the current segment info. */ + segT seg = now_seg; + subsegT subseg = now_subseg; + + for (s = stdoutput->sections; s; s = s->next) + for (frch = seg_info (s)->frchainP; frch; frch = frch->frch_next) + { + fragS *frag; + + for (frag = frch->frch_root; frag; frag = frag->fr_next) + { + if (frag->fr_type == rs_cfa) + { + expressionS exp; + expressionS *symval; + + symval = symbol_get_value_expression (frag->fr_symbol); + exp.X_op = O_subtract; + exp.X_add_symbol = symval->X_add_symbol; + exp.X_add_number = 0; + exp.X_op_symbol = symval->X_op_symbol; + + /* We must set the segment before creating a frag after all + frag chains have been chained together. */ + subseg_set (s, frch->frch_subseg); + + fix_new_exp (frag, (int) frag->fr_offset, 1, &exp, 0, + BFD_RELOC_LARCH_CFA); + } + } + } + + /* Restore the original segment info. */ + subseg_set (seg, subseg); +} + void tc_loongarch_parse_to_dw2regnum (expressionS *exp) { @@ -1343,6 +1593,58 @@ md_show_usage (FILE *stream) /* FIXME */ } +static void +loongarch_make_nops (char *buf, bfd_vma bytes) +{ + bfd_vma i = 0; + + /* Fill with 4-byte NOPs. */ + for ( ; i < bytes; i += 4) + number_to_chars_littleendian (buf + i, LARCH_NOP, 4); +} + +/* Called from md_do_align. Used to create an alignment frag in a + code section by emitting a worst-case NOP sequence that the linker + will later relax to the correct number of NOPs. We can't compute + the correct alignment now because of other linker relaxations. */ + +bool +loongarch_frag_align_code (int n) +{ + bfd_vma bytes = (bfd_vma) 1 << n; + bfd_vma insn_alignment = 4; + bfd_vma worst_case_bytes = bytes - insn_alignment; + char *nops; + expressionS ex; + + /* If we are moving to a smaller alignment than the instruction size, then no + alignment is required. */ + if (bytes <= insn_alignment) + return true; + + /* When not relaxing, loongarch_handle_align handles code alignment. */ + if (!LARCH_opts.relax) + return false; + + nops = frag_more (worst_case_bytes); + + ex.X_op = O_constant; + ex.X_add_number = worst_case_bytes; + + loongarch_make_nops (nops, worst_case_bytes); + + fix_new_exp (frag_now, nops - frag_now->fr_literal, 0, + &ex, false, BFD_RELOC_LARCH_ALIGN); + + /* We need to start a new frag after the alignment which may be removed by + the linker, to prevent the assembler from computing static offsets. + This is necessary to get correct EH info. */ + frag_wane (frag_now); + frag_new (0); + + return true; +} + /* Fill in an rs_align_code fragment. We want to fill 'andi $r0,$r0,0'. */ void loongarch_handle_align (fragS *fragp) @@ -1378,6 +1680,69 @@ loongarch_handle_align (fragS *fragp) fragp->fr_var = size; } +/* Scan uleb128 subtraction expressions and insert fixups for them. + e.g., .uleb128 .L1 - .L0 + Because relaxation may change the value of the subtraction, we + must resolve them at link-time. */ + +static void +loongarch_insert_uleb128_fixes (bfd *abfd ATTRIBUTE_UNUSED, + asection *sec, void *xxx ATTRIBUTE_UNUSED) +{ + segment_info_type *seginfo = seg_info (sec); + struct frag *fragP; + + subseg_set (sec, 0); + + for (fragP = seginfo->frchainP->frch_root; + fragP; fragP = fragP->fr_next) + { + expressionS *exp, *exp_dup; + + if (fragP->fr_type != rs_leb128 || fragP->fr_symbol == NULL) + continue; + + exp = symbol_get_value_expression (fragP->fr_symbol); + + if (exp->X_op != O_subtract) + continue; + + /* FIXME: Skip for .sleb128. */ + if (fragP->fr_subtype != 0) + continue; + + exp_dup = xmemdup (exp, sizeof (*exp), sizeof (*exp)); + exp_dup->X_op = O_symbol; + exp_dup->X_op_symbol = NULL; + + exp_dup->X_add_symbol = exp->X_add_symbol; + fix_new_exp (fragP, fragP->fr_fix, 0, + exp_dup, 0, BFD_RELOC_LARCH_ADD_ULEB128); + + /* From binutils/testsuite/binutils-all/dw5.S + section .debug_rnglists + .uleb128 .Letext0-.Ltext0 Range length (*.LLRL2) + Offset Info Type Symbol's Value Symbol's Name + Addend +0000000000000015 0000000200000079 R_LARCH_ADD_ULEB128 0000000000000000 .text + 2 +0000000000000015 000000020000007a R_LARCH_SUB_ULEB128 0000000000000000 .text + 0. */ + + /* Only the ADD_ULEB128 has X_add_number (Addend)? */ + exp_dup->X_add_number = 0; + exp_dup->X_add_symbol = exp->X_op_symbol; + fix_new_exp (fragP, fragP->fr_fix, 0, + exp_dup, 0, BFD_RELOC_LARCH_SUB_ULEB128); + } +} + +void +loongarch_md_finish (void) +{ + /* Insert relocations for uleb128 directives, so the values can be recomputed + at link time. */ + if (LARCH_opts.relax) + bfd_map_over_sections (stdoutput, loongarch_insert_uleb128_fixes, NULL); +} + void loongarch_elf_final_processing (void) { diff --git a/gas/config/tc-loongarch.h b/gas/config/tc-loongarch.h index 7d416b0c..cec50a4c 100644 --- a/gas/config/tc-loongarch.h +++ b/gas/config/tc-loongarch.h @@ -21,6 +21,8 @@ #ifndef TC_LOONGARCH #define TC_LOONGARCH +#include "opcode/loongarch.h" + #define TARGET_BYTES_BIG_ENDIAN 0 #define TARGET_ARCH bfd_arch_loongarch @@ -47,16 +49,63 @@ extern int loongarch_relax_frag (asection *, struct frag *, long); #define md_undefined_symbol(name) (0) #define md_operand(x) -/* This is called to see whether a reloc against a defined symbol - should be converted into a reloc against a section. */ -extern int loongarch_fix_adjustable (struct fix *fix); -#define tc_fix_adjustable(fixp) loongarch_fix_adjustable(fixp) +extern bool loongarch_frag_align_code (int); +#define md_do_align(N, FILL, LEN, MAX, LABEL) \ + if ((N) != 0 && !(FILL) && !need_pass_2 && subseg_text_p (now_seg)) \ + { \ + if (loongarch_frag_align_code (N)) \ + goto LABEL; \ + } + +/* The following two macros let the linker resolve all the relocs + due to relaxation. + + This is called to see whether a reloc against a defined symbol + should be converted into a reloc against a section. + + If relax and norelax have different value may cause ld ".eh_frame_hdr + refers to overlapping FDEs" error when link relax .o and norelax .o. */ +#define tc_fix_adjustable(fixp) 0 + +/* Tne difference between same-section symbols may be affected by linker + relaxation, so do not resolve such expressions in the assembler. */ +#define md_allow_local_subtract(l,r,s) 0 + +/* If subsy of BFD_RELOC32/64 and PC in same segment, and without relax + or PC at start of subsy or with relax but sub_symbol_segment not in + SEC_CODE, we generate 32/64_PCREL. */ +#define TC_FORCE_RELOCATION_SUB_LOCAL(FIX, SEG) \ + (!((BFD_RELOC_32 || BFD_RELOC_64) \ + &&(!LARCH_opts.relax \ + || S_GET_VALUE (FIX->fx_subsy) \ + == FIX->fx_frag->fr_address + FIX->fx_where \ + || (LARCH_opts.relax \ + && ((S_GET_SEGMENT (FIX->fx_subsy)->flags & SEC_CODE) == 0))))) -/* Values passed to md_apply_fix don't include symbol values. */ -#define TC_FORCE_RELOCATION_SUB_LOCAL(FIX, SEG) 1 #define TC_VALIDATE_FIX_SUB(FIX, SEG) 1 #define DIFF_EXPR_OK 1 +/* Postpone text-section label subtraction calculation until linking, since + linker relaxations might change the deltas. */ +#define TC_FORCE_RELOCATION_SUB_SAME(FIX, SEC) \ + (LARCH_opts.relax ? \ + (GENERIC_FORCE_RELOCATION_SUB_SAME (FIX, SEC) \ + || ((SEC)->flags & SEC_CODE) != 0 \ + || ((SEC)->flags & SEC_DEBUGGING) != 0 \ + || TC_FORCE_RELOCATION (FIX)) \ + : (GENERIC_FORCE_RELOCATION_SUB_SAME (FIX, SEC))) \ + +#define TC_LINKRELAX_FIXUP(seg) ((seg->flags & SEC_CODE) \ + || (seg->flags & SEC_DEBUGGING)) + +#define TC_FORCE_RELOCATION_LOCAL(FIX) 1 + +/* Adjust debug_line after relaxation. */ +#define DWARF2_USE_FIXED_ADVANCE_PC 1 + +/* Values passed to md_apply_fix don't include symbol values. */ +#define MD_APPLY_SYM_VALUE(FIX) 0 + #define TARGET_USE_CFIPOP 1 #define DWARF2_DEFAULT_RETURN_COLUMN 1 /* $ra. */ #define DWARF2_CIE_DATA_ALIGNMENT -4 @@ -65,13 +114,16 @@ extern int loongarch_fix_adjustable (struct fix *fix); loongarch_cfi_frame_initial_instructions extern void loongarch_cfi_frame_initial_instructions (void); +#define tc_symbol_new_hook(sym) \ + if (0 == strcmp (sym->bsym->name, FAKE_LABEL_NAME)) \ + S_SET_OTHER (sym, STV_HIDDEN); + #define tc_parse_to_dw2regnum tc_loongarch_parse_to_dw2regnum extern void tc_loongarch_parse_to_dw2regnum (expressionS *); -/* A enumerated values to specific how to deal with align in '.text'. - Now we want to fill 'andi $r0,$r0,0x0'. - Here is the type 0, will fill andi insn later. */ -#define NOP_OPCODE (0x00) +extern void loongarch_pre_output_hook (void); +#define md_pre_output_hook loongarch_pre_output_hook () +#define GAS_SORT_RELOCS 1 #define SUB_SEGMENT_ALIGN(SEG, FRCHAIN) 0 @@ -90,4 +142,7 @@ struct reloc_info expressionS value; }; +#define md_end loongarch_md_finish +extern void loongarch_md_finish (void); + #endif diff --git a/gas/ehopt.c b/gas/ehopt.c index 21f0755b..95fbfdf7 100644 --- a/gas/ehopt.c +++ b/gas/ehopt.c @@ -384,7 +384,7 @@ check_eh_frame (expressionS *exp, unsigned int *pnbytes) { /* This might be a DW_CFA_advance_loc4. Record the frag and the position within the frag, so that we can change it later. */ - frag_grow (1); + frag_grow (1 + 4); d->state = state_saw_loc4; d->loc4_frag = frag_now; d->loc4_fix = frag_now_fix (); diff --git a/gas/testsuite/gas/all/align.d b/gas/testsuite/gas/all/align.d index c701f25b..43c1413d 100644 --- a/gas/testsuite/gas/all/align.d +++ b/gas/testsuite/gas/all/align.d @@ -3,8 +3,9 @@ # The RX port will always replace zeros in any aligned area with NOPs, # even if the user requested that they filled with zeros. # RISC-V handles alignment via relaxation and therefor won't have object files -# with the expected alignment. -#notarget: riscv*-* rx-* +# LoongArch handles alignment via relaxation and therefor won't have object +# files with the expected alignment. +#notarget: loongarch*-* riscv*-* rx-* # Test the alignment pseudo-op. diff --git a/gas/testsuite/gas/all/gas.exp b/gas/testsuite/gas/all/gas.exp index b39acfa0..3968fbbe 100644 --- a/gas/testsuite/gas/all/gas.exp +++ b/gas/testsuite/gas/all/gas.exp @@ -62,14 +62,14 @@ if { ![istarget alpha*-*-*vms*] && ![istarget ft32-*-*] && ![istarget hppa*-*-*] && ![istarget microblaze-*-*] + && ![istarget loongarch*-*-*] && ![istarget mn10300-*-*] && ![istarget msp430*-*-*] && ![istarget powerpc*-*-aix*] && ![istarget riscv*-*-*] && ![istarget rl78-*-*] && ![istarget rs6000*-*-aix*] - && ![istarget rx-*-*] - && ![istarget loongarch*-*-*] } then { + && ![istarget rx-*-*] } then { gas_test_error "diff1.s" "" "difference of two undefined symbols" } @@ -160,10 +160,10 @@ switch -glob $target_triplet { # These targets fail redef2 because they disallow redefined # symbols on relocs. setup_xfail "m68hc1*-*-*" "m6811-*-*" "m6812-*-*" "rl78-*-*" - setup_xfail "riscv*-*-*" "rx-*-*" "vax*-*-*" "xgate*-*-*" "z8k-*-*" + setup_xfail "loongarch*-*-*" "riscv*-*-*" "rx-*-*" "vax*-*-*" "xgate*-*-*" "z8k-*-*" run_dump_test redef2 setup_xfail "m68hc1*-*-*" "m6811-*-*" "m6812-*-*" "rl78-*-*" - setup_xfail "riscv*-*-*" "rx-*-*" "vax*-*-*" "xgate*-*-*" "z8k-*-*" + setup_xfail "loongarch*-*-*" "riscv*-*-*" "rx-*-*" "vax*-*-*" "xgate*-*-*" "z8k-*-*" # rs6000-aix disallows redefinition via .comm. if [is_xcoff_format] { setup_xfail *-*-* @@ -274,7 +274,7 @@ if { ![istarget *c30*-*-*] # The vax fails because VMS can apparently actually handle this # case in relocs, so gas doesn't handle it itself. # msp430, mn10[23]00 and riscv emit two relocs to handle the difference of two symbols. - setup_xfail "am3*-*-*" "mn10200-*-*" "mn10300*-*-*" "msp430*-*-*" "riscv*-*-*" "vax*-*-vms*" + setup_xfail "am3*-*-*" "loongarch*-*-*" "mn10200-*-*" "mn10300*-*-*" "msp430*-*-*" "riscv*-*-*" "vax*-*-vms*" do_930509a } diff --git a/gas/testsuite/gas/all/relax.d b/gas/testsuite/gas/all/relax.d index f394043b..00fba6d6 100644 --- a/gas/testsuite/gas/all/relax.d +++ b/gas/testsuite/gas/all/relax.d @@ -4,6 +4,10 @@ # because symbol values are not known until after linker relaxation has been # performed. #notarget : riscv*-*-* +# LoongArch doesn't resolve .uleb operands that are the difference of two +# symbols because gas write zero to object file and generate add_uleb128 and +# sub_uleb128 reloc pair. +#xfail: loongarch*-*-* .*: .* diff --git a/gas/testsuite/gas/elf/dwarf2-11.d b/gas/testsuite/gas/elf/dwarf2-11.d index 2c30e55c..44f5cd18 100644 --- a/gas/testsuite/gas/elf/dwarf2-11.d +++ b/gas/testsuite/gas/elf/dwarf2-11.d @@ -3,7 +3,8 @@ #name: DWARF2 11 # The am33 cr16 crx ft32 mn10 msp430 nds32 and rl78 targets do not evaluate the subtraction of symbols at assembly time. # The riscv targets do not support the subtraction of symbols. -#xfail: am3*-* cr16-* crx-* ft32*-* mn10*-* msp430-* nds32*-* riscv*-* rl78-* +# The loongarch targets do not support the subtraction of symbols. +#xfail: am3*-* cr16-* crx-* ft32*-* loongarch*-* mn10*-* msp430-* nds32*-* riscv*-* rl78-* Contents of the \.debug_line section: diff --git a/gas/testsuite/gas/elf/dwarf2-15.d b/gas/testsuite/gas/elf/dwarf2-15.d index 939c6159..3ec9f278 100644 --- a/gas/testsuite/gas/elf/dwarf2-15.d +++ b/gas/testsuite/gas/elf/dwarf2-15.d @@ -3,7 +3,8 @@ #name: DWARF2 15 # The am33 cr16 crx ft32 mn10 msp430 nds32 and rl78 targets do not evaluate the subtraction of symbols at assembly time. # The riscv targets do not support the subtraction of symbols. -#xfail: am3*-* cr16-* crx-* ft32*-* mn10*-* msp430-* nds32*-* riscv*-* rl78-* +# The loongarch targets do not support the subtraction of symbols. +#xfail: am3*-* cr16-* crx-* ft32*-* loongarch*-* mn10*-* msp430-* nds32*-* riscv*-* rl78-* Hex dump of section '\.rodata': 0x00000000 01 *.* diff --git a/gas/testsuite/gas/elf/dwarf2-16.d b/gas/testsuite/gas/elf/dwarf2-16.d index 8e35d493..32b57763 100644 --- a/gas/testsuite/gas/elf/dwarf2-16.d +++ b/gas/testsuite/gas/elf/dwarf2-16.d @@ -4,7 +4,8 @@ # The am33 cr16 crx ft32 mn10 msp430 nds32 and rl78 targets do not evaluate the subtraction of symbols at assembly time. # The mep target tries to relay code sections which breaks symbolic view computations. # The riscv targets do not support the subtraction of symbols. -#xfail: am3*-* cr16-* crx-* ft32*-* mep-* mn10*-* msp430-* nds32*-* riscv*-* rl78-* +# The loongarch targets do not support the subtraction of symbols. +#xfail: am3*-* cr16-* crx-* ft32*-* mep-* loongarch*-* mn10*-* msp430-* nds32*-* riscv*-* rl78-* Hex dump of section '\.rodata': 0x00000000 01 *.* diff --git a/gas/testsuite/gas/elf/dwarf2-17.d b/gas/testsuite/gas/elf/dwarf2-17.d index 881477cf..4c2f2e39 100644 --- a/gas/testsuite/gas/elf/dwarf2-17.d +++ b/gas/testsuite/gas/elf/dwarf2-17.d @@ -4,7 +4,8 @@ # The am33 cr16 crx ft32 mn10 msp430 nds32 and rl78 targets do not evaluate the subtraction of symbols at assembly time. # The mep target tries to relay code sections which breaks symbolic view computations. # The riscv targets do not support the subtraction of symbols. -#xfail: am3*-* cr16-* crx-* ft32*-* mep-* mn10*-* msp430-* nds32*-* riscv*-* rl78-* +# The loongarch targets do not support the subtraction of symbols. +#xfail: am3*-* cr16-* crx-* ft32*-* loongarch*-* mep-* mn10*-* msp430-* nds32*-* riscv*-* rl78-* Hex dump of section '\.rodata': 0x00000000 00 *.* diff --git a/gas/testsuite/gas/elf/dwarf2-18.d b/gas/testsuite/gas/elf/dwarf2-18.d index db7a4f9f..60c7d750 100644 --- a/gas/testsuite/gas/elf/dwarf2-18.d +++ b/gas/testsuite/gas/elf/dwarf2-18.d @@ -4,7 +4,8 @@ # The am33 cr16 crx ft32 mn10 msp430 nds32 and rl78 targets do not evaluate the subtraction of symbols at assembly time. # The mep targets turns some view computations into complex relocations. # The riscv targets do not support the subtraction of symbols. -#xfail: am3*-* cr16-* crx-* ft32*-* mep-* mn10*-* msp430-* nds32*-* riscv*-* rl78-* +# The loongarch targets do not support the subtraction of symbols. +#xfail: am3*-* cr16-* crx-* ft32*-* loongarch*-* mn10*-* msp430-* nds32*-* riscv*-* rl78-* Hex dump of section '\.rodata': 0x00000000 0100 *.* diff --git a/gas/testsuite/gas/elf/dwarf2-19.d b/gas/testsuite/gas/elf/dwarf2-19.d index 55d0caf4..133294af 100644 --- a/gas/testsuite/gas/elf/dwarf2-19.d +++ b/gas/testsuite/gas/elf/dwarf2-19.d @@ -4,7 +4,8 @@ # The am33 cr16 crx ft32 mn10 msp430 nds32 and rl78 targets do not evaluate the subtraction of symbols at assembly time. # The mep targets turns some view computations into complex relocations. # The riscv targets do not support the subtraction of symbols. -#xfail: am3*-* cr16-* crx-* ft32*-* mep-* mn10*-* msp430-* nds32*-* riscv*-* rl78-* +# The loongarch targets do not support the subtraction of symbols. +#xfail: am3*-* cr16-* crx-* ft32*-* mep-* loongarch*-* mn10*-* msp430-* nds32*-* riscv*-* rl78-* Hex dump of section '\.rodata': 0x00000000 01000102 *.* diff --git a/gas/testsuite/gas/elf/dwarf2-5.d b/gas/testsuite/gas/elf/dwarf2-5.d index 257bb55a..3bc7c9e0 100644 --- a/gas/testsuite/gas/elf/dwarf2-5.d +++ b/gas/testsuite/gas/elf/dwarf2-5.d @@ -4,7 +4,8 @@ # The am33 cr16 crx ft32 mn10 msp430 nds32 rl78 and rx targets do not evaluate the subtraction of symbols at assembly time. # The mep target tries to relay code sections which breaks symbolic view computations. # The riscv targets do not support the subtraction of symbols. -#xfail: am3*-* cr16-* crx-* ft32*-* mep-* mn10*-* msp430-* nds32*-* riscv*-* rl78-* rx-* +# The loongarch targets do not support the subtraction of symbols. +#xfail: am3*-* cr16-* crx-* ft32*-* loongarch*-* mep-* mn10*-* msp430-* nds32*-* riscv*-* rl78-* rx-* Hex dump of section '\.rodata': 0x00000000 01010201 010203 *.* diff --git a/gas/testsuite/gas/elf/ehopt0.d b/gas/testsuite/gas/elf/ehopt0.d index a13c4f26..64c5fb5d 100644 --- a/gas/testsuite/gas/elf/ehopt0.d +++ b/gas/testsuite/gas/elf/ehopt0.d @@ -1,5 +1,8 @@ #objdump: -s -j .eh_frame #name: elf ehopt0 +# The loongarch target do not evaluate .eh_frame fde cfa advance loc at assembly time. +# Because loongarch use add/sub reloc evaluate cfa advance loc, so gas should write 0 to cfa advance loc address. +#xfail: loongarch*-* .*: +file format .* diff --git a/gas/testsuite/gas/elf/elf.exp b/gas/testsuite/gas/elf/elf.exp index 20a4ada4..0a2717bb 100644 --- a/gas/testsuite/gas/elf/elf.exp +++ b/gas/testsuite/gas/elf/elf.exp @@ -72,6 +72,9 @@ if { [is_elf_format] } then { if {[istarget "csky*-*-*"]} { set target_machine -csky } + if {[istarget "loongarch*-*-*"]} then { + set dump_opts {{as -mno-relax}} + } if {[istarget "m32r*-*-*"]} then { set target_machine -m32r } diff --git a/gas/testsuite/gas/elf/section11.d b/gas/testsuite/gas/elf/section11.d index 427aea67..277fa6df 100644 --- a/gas/testsuite/gas/elf/section11.d +++ b/gas/testsuite/gas/elf/section11.d @@ -2,8 +2,8 @@ #readelf: -S --wide #name: Disabling section padding # The RX port uses non standard section names. -#xfail: rx-*-* -# RISC-V handles alignment via linker relaxation, so object files don't have +#xfail: loongarch*-* rx-*-* +# LoongArch and RISC-V handles alignment via linker relaxation, so object files don't have # the expected alignment. #xfail: riscv*-*-* diff --git a/gas/testsuite/gas/lns/lns.exp b/gas/testsuite/gas/lns/lns.exp index 7eabc1b8..838f07ce 100644 --- a/gas/testsuite/gas/lns/lns.exp +++ b/gas/testsuite/gas/lns/lns.exp @@ -31,6 +31,7 @@ if { ![istarget s390*-*-*] } { || [istarget cr16-*-*] || [istarget crx-*-*] || [istarget ft32*-*] + || [istarget loongarch*-*-*] || [istarget mn10*-*-*] || [istarget msp430-*-*] || [istarget nds32*-*-*] diff --git a/gas/testsuite/gas/loongarch/64_pcrel.d b/gas/testsuite/gas/loongarch/64_pcrel.d new file mode 100644 index 00000000..66b80a39 --- /dev/null +++ b/gas/testsuite/gas/loongarch/64_pcrel.d @@ -0,0 +1,11 @@ +#as: +#objdump: -dr + +.*:[ ]+file format .* + + +Disassembly of section .text: + +00000000.* <.text>: +[ ]+0:[ ]+03400000[ ]+nop[ ]+ +[ ]+0:[ ]+R_LARCH_64_PCREL[ ]+\*ABS\* diff --git a/gas/testsuite/gas/loongarch/64_pcrel.s b/gas/testsuite/gas/loongarch/64_pcrel.s new file mode 100644 index 00000000..932e1bf2 --- /dev/null +++ b/gas/testsuite/gas/loongarch/64_pcrel.s @@ -0,0 +1,2 @@ +nop +.reloc 0, R_LARCH_64_PCREL, 0 diff --git a/gas/testsuite/gas/loongarch/deprecated_reg_aliases.d b/gas/testsuite/gas/loongarch/deprecated_reg_aliases.d new file mode 100644 index 00000000..3ea08067 --- /dev/null +++ b/gas/testsuite/gas/loongarch/deprecated_reg_aliases.d @@ -0,0 +1,18 @@ +#name: Deprecated register aliases +#as-new: +#objdump: -d +#warning_output: deprecated_reg_aliases.l +#skip: loongarch32-*-* + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0000000000000000 <foo>: +[ ]+0:[ ]+14acf125[ ]+lu12i\.w[ ]+\$a1, 354185 +[ ]+4:[ ]+038048a5[ ]+ori[ ]+\$a1, \$a1, 0x12 +[ ]+8:[ ]+16024685[ ]+lu32i\.d[ ]+\$a1, 4660 +[ ]+c:[ ]+08200420[ ]+fmadd\.d[ ]+\$fa0, \$fa1, \$fa1, \$fa0 +[ ]+10:[ ]+380c16a4[ ]+ldx\.d[ ]+\$a0, \$r21, \$a1 +[ ]+14:[ ]+4c000020[ ]+ret[ ]+ diff --git a/gas/testsuite/gas/loongarch/deprecated_reg_aliases.l b/gas/testsuite/gas/loongarch/deprecated_reg_aliases.l new file mode 100644 index 00000000..b82c209e --- /dev/null +++ b/gas/testsuite/gas/loongarch/deprecated_reg_aliases.l @@ -0,0 +1,7 @@ +.*Assembler messages: +.*:2: Warning: register alias \$v1 is deprecated, use \$a1 instead +.*:3: Warning: register alias \$fv0 is deprecated, use \$fa0 instead +.*:3: Warning: register alias \$fv1 is deprecated, use \$fa1 instead +.*:3: Warning: register alias \$fv1 is deprecated, use \$fa1 instead +.*:4: Warning: register alias \$v0 is deprecated, use \$a0 instead +.*:4: Warning: register alias \$x is deprecated, use \$r21 instead diff --git a/gas/testsuite/gas/loongarch/deprecated_reg_aliases.s b/gas/testsuite/gas/loongarch/deprecated_reg_aliases.s new file mode 100644 index 00000000..7848346e --- /dev/null +++ b/gas/testsuite/gas/loongarch/deprecated_reg_aliases.s @@ -0,0 +1,5 @@ +foo: + li.d $v1, 0x123456789012 + fmadd.d $fv0, $fv1, $fv1, $fa0 + ldx.d $v0, $x, $a1 + ret diff --git a/gas/testsuite/gas/loongarch/float_op.d b/gas/testsuite/gas/loongarch/float_op.d index cdc41d4d..f9d3b89e 100644 --- a/gas/testsuite/gas/loongarch/float_op.d +++ b/gas/testsuite/gas/loongarch/float_op.d @@ -49,8 +49,8 @@ Disassembly of section .text: [ ]+9c:[ ]+0114b424 [ ]+movfr2gr.s[ ]+[ ]+\$a0, \$fa1 [ ]+a0:[ ]+0114b824 [ ]+movfr2gr.d[ ]+[ ]+\$a0, \$fa1 [ ]+a4:[ ]+0114bc24 [ ]+movfrh2gr.s [ ]+\$a0, \$fa1 -[ ]+a8:[ ]+0114c0a4 [ ]+movgr2fcsr[ ]+[ ]+\$a0, \$a1 -[ ]+ac:[ ]+0114c8a4 [ ]+movfcsr2gr[ ]+[ ]+\$a0, \$a1 +[ ]+a8:[ ]+0114c0a0 [ ]+movgr2fcsr[ ]+[ ]+\$fcsr0, \$a1 +[ ]+ac:[ ]+0114c804 [ ]+movfcsr2gr[ ]+[ ]+\$a0, \$fcsr0 [ ]+b0:[ ]+0114d020 [ ]+movfr2cf[ ]+[ ]+\$fcc0, \$fa1 [ ]+b4:[ ]+0114d4a0 [ ]+movcf2fr[ ]+[ ]+\$fa0, \$fcc5 [ ]+b8:[ ]+0114d8a0 [ ]+movgr2cf[ ]+[ ]+\$fcc0, \$a1 diff --git a/gas/testsuite/gas/loongarch/float_op.s b/gas/testsuite/gas/loongarch/float_op.s index da1a198e..2e3ec5b8 100644 --- a/gas/testsuite/gas/loongarch/float_op.s +++ b/gas/testsuite/gas/loongarch/float_op.s @@ -40,8 +40,8 @@ movgr2frh.w $f0,$r5 movfr2gr.s $r4,$f1 movfr2gr.d $r4,$f1 movfrh2gr.s $r4,$f1 -movgr2fcsr $r4,$r5 -movfcsr2gr $r4,$r5 +movgr2fcsr $fcsr0,$r5 +movfcsr2gr $r4,$fcsr0 movfr2cf $fcc0,$f1 movcf2fr $f0,$fcc5 movgr2cf $fcc0,$r5 diff --git a/gas/testsuite/gas/loongarch/imm_ins.d b/gas/testsuite/gas/loongarch/imm_ins.d new file mode 100644 index 00000000..f00110cd --- /dev/null +++ b/gas/testsuite/gas/loongarch/imm_ins.d @@ -0,0 +1,80 @@ +#as: +#objdump: -dr +#skip: loongarch32-*-* + +.*:[ ]+file format .* + + +Disassembly of section .text: + +00000000.* <.text>: +[ ]+0:[ ]+03848c0c[ ]+li.w[ ]+\$t0,[ ]+0x123 +[ ]+4:[ ]+15ffe00d[ ]+lu12i.w[ ]+\$t1,[ ]+-256 +[ ]+8:[ ]+16001fed[ ]+lu32i.d[ ]+\$t1,[ ]+255 +[ ]+c:[ ]+02bffc0e[ ]+li.w[ ]+\$t2,[ ]+-1 +[ ]+10:[ ]+1601ffee[ ]+lu32i.d[ ]+\$t2,[ ]+4095 +[ ]+14:[ ]+0004b58b[ ]+alsl.w[ ]+\$a7,[ ]+\$t0,[ ]+\$t1,[ ]+0x2 +[ ]+18:[ ]+0006b58b[ ]+alsl.wu[ ]+\$a7,[ ]+\$t0,[ ]+\$t1,[ ]+0x2 +[ ]+1c:[ ]+0009358b[ ]+bytepick.w[ ]+\$a7,[ ]+\$t0,[ ]+\$t1,[ ]+0x2 +[ ]+20:[ ]+000d358b[ ]+bytepick.d[ ]+\$a7,[ ]+\$t0,[ ]+\$t1,[ ]+0x2 +[ ]+24:[ ]+002a0002[ ]+break[ ]+0x2 +[ ]+28:[ ]+002a8002[ ]+dbcl[ ]+0x2 +[ ]+2c:[ ]+002b0002[ ]+syscall[ ]+0x2 +[ ]+30:[ ]+002cb58b[ ]+alsl.d[ ]+\$a7,[ ]+\$t0,[ ]+\$t1,[ ]+0x2 +[ ]+34:[ ]+0040898b[ ]+slli.w[ ]+\$a7,[ ]+\$t0,[ ]+0x2 +[ ]+38:[ ]+0041098b[ ]+slli.d[ ]+\$a7,[ ]+\$t0,[ ]+0x2 +[ ]+3c:[ ]+0044898b[ ]+srli.w[ ]+\$a7,[ ]+\$t0,[ ]+0x2 +[ ]+40:[ ]+004509ac[ ]+srli.d[ ]+\$t0,[ ]+\$t1,[ ]+0x2 +[ ]+44:[ ]+004889ac[ ]+srai.w[ ]+\$t0,[ ]+\$t1,[ ]+0x2 +[ ]+48:[ ]+004909ac[ ]+srai.d[ ]+\$t0,[ ]+\$t1,[ ]+0x2 +[ ]+4c:[ ]+006209ac[ ]+bstrins.w[ ]+\$t0,[ ]+\$t1,[ ]+0x2,[ ]+0x2 +[ ]+50:[ ]+008209ac[ ]+bstrins.d[ ]+\$t0,[ ]+\$t1,[ ]+0x2,[ ]+0x2 +[ ]+54:[ ]+00c209ac[ ]+bstrpick.d[ ]+\$t0,[ ]+\$t1,[ ]+0x2,[ ]+0x2 +[ ]+58:[ ]+00c209ac[ ]+bstrpick.d[ ]+\$t0,[ ]+\$t1,[ ]+0x2,[ ]+0x2 +[ ]+5c:[ ]+02048dac[ ]+slti[ ]+\$t0,[ ]+\$t1,[ ]+291 +[ ]+60:[ ]+02448dac[ ]+sltui[ ]+\$t0,[ ]+\$t1,[ ]+291 +[ ]+64:[ ]+02848dac[ ]+addi.w[ ]+\$t0,[ ]+\$t1,[ ]+291 +[ ]+68:[ ]+02c48dac[ ]+addi.d[ ]+\$t0,[ ]+\$t1,[ ]+291 +[ ]+6c:[ ]+03048dac[ ]+lu52i.d[ ]+\$t0,[ ]+\$t1,[ ]+291 +[ ]+70:[ ]+034009ac[ ]+andi[ ]+\$t0,[ ]+\$t1,[ ]+0x2 +[ ]+74:[ ]+038009ac[ ]+ori[ ]+\$t0,[ ]+\$t1,[ ]+0x2 +[ ]+78:[ ]+03c009ac[ ]+xori[ ]+\$t0,[ ]+\$t1,[ ]+0x2 +[ ]+7c:[ ]+100009ac[ ]+addu16i.d[ ]+\$t0,[ ]+\$t1,[ ]+2 +[ ]+80:[ ]+1400246c[ ]+lu12i.w[ ]+\$t0,[ ]+291 +[ ]+84:[ ]+1600246c[ ]+lu32i.d[ ]+\$t0,[ ]+291 +[ ]+88:[ ]+1800246c[ ]+pcaddi[ ]+\$t0,[ ]+291 +[ ]+8c:[ ]+1a00246c[ ]+pcalau12i[ ]+\$t0,[ ]+291 +[ ]+90:[ ]+1c00246c[ ]+pcaddu12i[ ]+\$t0,[ ]+291 +[ ]+94:[ ]+1e00246c[ ]+pcaddu18i[ ]+\$t0,[ ]+291 +[ ]+98:[ ]+04048c0c[ ]+csrrd[ ]+\$t0,[ ]+0x123 +[ ]+9c:[ ]+04048c2c[ ]+csrwr[ ]+\$t0,[ ]+0x123 +[ ]+a0:[ ]+040009ac[ ]+csrxchg[ ]+\$t0,[ ]+\$t1,[ ]+0x2 +[ ]+a4:[ ]+060009a2[ ]+cacop[ ]+0x2,[ ]+\$t1,[ ]+2 +[ ]+a8:[ ]+064009ac[ ]+lddir[ ]+\$t0,[ ]+\$t1,[ ]+0x2 +[ ]+ac:[ ]+06440980[ ]+ldpte[ ]+\$t0,[ ]+0x2 +[ ]+b0:[ ]+0649b9a2[ ]+invtlb[ ]+0x2,[ ]+\$t1,[ ]+\$t2 +[ ]+b4:[ ]+200101ac[ ]+ll.w[ ]+\$t0,[ ]+\$t1,[ ]+256 +[ ]+b8:[ ]+210101ac[ ]+sc.w[ ]+\$t0,[ ]+\$t1,[ ]+256 +[ ]+bc:[ ]+220101ac[ ]+ll.d[ ]+\$t0,[ ]+\$t1,[ ]+256 +[ ]+c0:[ ]+230101ac[ ]+sc.d[ ]+\$t0,[ ]+\$t1,[ ]+256 +[ ]+c4:[ ]+240101ac[ ]+ldptr.w[ ]+\$t0,[ ]+\$t1,[ ]+256 +[ ]+c8:[ ]+250101ac[ ]+stptr.w[ ]+\$t0,[ ]+\$t1,[ ]+256 +[ ]+cc:[ ]+260101ac[ ]+ldptr.d[ ]+\$t0,[ ]+\$t1,[ ]+256 +[ ]+d0:[ ]+270101ac[ ]+stptr.d[ ]+\$t0,[ ]+\$t1,[ ]+256 +[ ]+d4:[ ]+280401ac[ ]+ld.b[ ]+\$t0,[ ]+\$t1,[ ]+256 +[ ]+d8:[ ]+284401ac[ ]+ld.h[ ]+\$t0,[ ]+\$t1,[ ]+256 +[ ]+dc:[ ]+288401ac[ ]+ld.w[ ]+\$t0,[ ]+\$t1,[ ]+256 +[ ]+e0:[ ]+28c401ac[ ]+ld.d[ ]+\$t0,[ ]+\$t1,[ ]+256 +[ ]+e4:[ ]+290401ac[ ]+st.b[ ]+\$t0,[ ]+\$t1,[ ]+256 +[ ]+e8:[ ]+294401ac[ ]+st.h[ ]+\$t0,[ ]+\$t1,[ ]+256 +[ ]+ec:[ ]+298401ac[ ]+st.w[ ]+\$t0,[ ]+\$t1,[ ]+256 +[ ]+f0:[ ]+29c401ac[ ]+st.d[ ]+\$t0,[ ]+\$t1,[ ]+256 +[ ]+f4:[ ]+2a0401ac[ ]+ld.bu[ ]+\$t0,[ ]+\$t1,[ ]+256 +[ ]+f8:[ ]+2a4401ac[ ]+ld.hu[ ]+\$t0,[ ]+\$t1,[ ]+256 +[ ]+fc:[ ]+2a8401ac[ ]+ld.wu[ ]+\$t0,[ ]+\$t1,[ ]+256 +[ ]+100:[ ]+2ac401a2[ ]+preld[ ]+0x2,[ ]+\$t1,[ ]+256 +[ ]+104:[ ]+382c39a2[ ]+preldx[ ]+0x2,[ ]+\$t1,[ ]+\$t2 +[ ]+108:[ ]+2b048d8a[ ]+fld.s[ ]+\$ft2,[ ]+\$t0,[ ]+291 +[ ]+10c:[ ]+2b448d8a[ ]+fst.s[ ]+\$ft2,[ ]+\$t0,[ ]+291 +[ ]+110:[ ]+2b848d8a[ ]+fld.d[ ]+\$ft2,[ ]+\$t0,[ ]+291 +[ ]+114:[ ]+2bc48d8a[ ]+fst.d[ ]+\$ft2,[ ]+\$t0,[ ]+291 diff --git a/gas/testsuite/gas/loongarch/imm_ins.s b/gas/testsuite/gas/loongarch/imm_ins.s new file mode 100644 index 00000000..f6a4e745 --- /dev/null +++ b/gas/testsuite/gas/loongarch/imm_ins.s @@ -0,0 +1,83 @@ +.equ a, 0x123 +.equ b, 0xfffff00000 +.equ c, 0xfffffffffff +.equ d, 2 +.equ e,0x100 + +li.w $r12, a +li.d $r13, b +li.d $r14, c + +alsl.w $r11,$r12,$r13,d +alsl.wu $r11,$r12,$r13,d +bytepick.w $r11,$r12,$r13,d +bytepick.d $r11,$r12,$r13,d + +break d +dbcl d +syscall d + +alsl.d $r11,$r12, $r13,d +slli.w $r11,$r12,d +slli.d $r11,$r12,d +srli.w $r11,$r12,d +srli.d $r12,$r13,d +srai.w $r12,$r13,d +srai.d $r12,$r13,d + +bstrins.w $r12,$r13,d,d +bstrins.d $r12,$r13,d,d +bstrpick.d $r12,$r13,d,d +bstrpick.d $r12,$r13,d,d + +slti $r12,$r13,a +sltui $r12,$r13,a +addi.w $r12,$r13,a +addi.d $r12,$r13,a +lu52i.d $r12,$r13,a +andi $r12,$r13,d +ori $r12,$r13,d +xori $r12,$r13,d +addu16i.d $r12,$r13,d +lu12i.w $r12,a +lu32i.d $r12,a +pcaddi $r12,a +pcalau12i $r12,a +pcaddu12i $r12,a +pcaddu18i $r12,a + +csrrd $r12,a +csrwr $r12,a +csrxchg $r12,$r13,d +cacop d,$r13,d +lddir $r12,$r13,d +ldpte $r12,d + +invtlb d,$r13,$r14 + +ll.w $r12,$r13,e +sc.w $r12,$r13,e +ll.d $r12,$r13,e +sc.d $r12,$r13,e +ldptr.w $r12,$r13,e +stptr.w $r12,$r13,e +ldptr.d $r12,$r13,e +stptr.d $r12,$r13,e +ld.b $r12,$r13,e +ld.h $r12,$r13,e +ld.w $r12,$r13,e +ld.d $r12,$r13,e +st.b $r12,$r13,e +st.h $r12,$r13,e +st.w $r12,$r13,e +st.d $r12,$r13,e +ld.bu $r12,$r13,e +ld.hu $r12,$r13,e +ld.wu $r12,$r13,e +preld d,$r13,e +preldx d,$r13,$r14 + +fld.s $f10,$r12,a +fst.s $f10,$r12,a +fld.d $f10,$r12,a +fst.d $f10,$r12,a diff --git a/gas/testsuite/gas/loongarch/imm_ins_32.d b/gas/testsuite/gas/loongarch/imm_ins_32.d new file mode 100644 index 00000000..dc2eeb9e --- /dev/null +++ b/gas/testsuite/gas/loongarch/imm_ins_32.d @@ -0,0 +1,57 @@ +#as: +#objdump: -dr +#skip: loongarch64-*-* + +.*:[ ]+file format .* + + +Disassembly of section .text: + +00000000.* <.text>: +[ ]+0:[ ]+03848c0c[ ]+li.w[ ]+\$t0,[ ]+0x123 +[ ]+4:[ ]+0004b58b[ ]+alsl.w[ ]+\$a7,[ ]+\$t0,[ ]+\$t1,[ ]+0x2 +[ ]+8:[ ]+0006b58b[ ]+alsl.wu[ ]+\$a7,[ ]+\$t0,[ ]+\$t1,[ ]+0x2 +[ ]+c:[ ]+0009358b[ ]+bytepick.w[ ]+\$a7,[ ]+\$t0,[ ]+\$t1,[ ]+0x2 +[ ]+10:[ ]+002a0002[ ]+break[ ]+0x2 +[ ]+14:[ ]+002a8002[ ]+dbcl[ ]+0x2 +[ ]+18:[ ]+002b0002[ ]+syscall[ ]+0x2 +[ ]+1c:[ ]+0040898b[ ]+slli.w[ ]+\$a7,[ ]+\$t0,[ ]+0x2 +[ ]+20:[ ]+0044898b[ ]+srli.w[ ]+\$a7,[ ]+\$t0,[ ]+0x2 +[ ]+24:[ ]+004889ac[ ]+srai.w[ ]+\$t0,[ ]+\$t1,[ ]+0x2 +[ ]+28:[ ]+006209ac[ ]+bstrins.w[ ]+\$t0,[ ]+\$t1,[ ]+0x2,[ ]+0x2 +[ ]+2c:[ ]+02048dac[ ]+slti[ ]+\$t0,[ ]+\$t1,[ ]+291 +[ ]+30:[ ]+02448dac[ ]+sltui[ ]+\$t0,[ ]+\$t1,[ ]+291 +[ ]+34:[ ]+02848dac[ ]+addi.w[ ]+\$t0,[ ]+\$t1,[ ]+291 +[ ]+38:[ ]+034009ac[ ]+andi[ ]+\$t0,[ ]+\$t1,[ ]+0x2 +[ ]+3c:[ ]+038009ac[ ]+ori[ ]+\$t0,[ ]+\$t1,[ ]+0x2 +[ ]+40:[ ]+03c009ac[ ]+xori[ ]+\$t0,[ ]+\$t1,[ ]+0x2 +[ ]+44:[ ]+1400246c[ ]+lu12i.w[ ]+\$t0,[ ]+291 +[ ]+48:[ ]+1800246c[ ]+pcaddi[ ]+\$t0,[ ]+291 +[ ]+4c:[ ]+1a00246c[ ]+pcalau12i[ ]+\$t0,[ ]+291 +[ ]+50:[ ]+1c00246c[ ]+pcaddu12i[ ]+\$t0,[ ]+291 +[ ]+54:[ ]+1e00246c[ ]+pcaddu18i[ ]+\$t0,[ ]+291 +[ ]+58:[ ]+04048c0c[ ]+csrrd[ ]+\$t0,[ ]+0x123 +[ ]+5c:[ ]+04048c2c[ ]+csrwr[ ]+\$t0,[ ]+0x123 +[ ]+60:[ ]+040009ac[ ]+csrxchg[ ]+\$t0,[ ]+\$t1,[ ]+0x2 +[ ]+64:[ ]+060009a2[ ]+cacop[ ]+0x2,[ ]+\$t1,[ ]+2 +[ ]+68:[ ]+064009ac[ ]+lddir[ ]+\$t0,[ ]+\$t1,[ ]+0x2 +[ ]+6c:[ ]+06440980[ ]+ldpte[ ]+\$t0,[ ]+0x2 +[ ]+70:[ ]+0649b9a2[ ]+invtlb[ ]+0x2,[ ]+\$t1,[ ]+\$t2 +[ ]+74:[ ]+200101ac[ ]+ll.w[ ]+\$t0,[ ]+\$t1,[ ]+256 +[ ]+78:[ ]+210101ac[ ]+sc.w[ ]+\$t0,[ ]+\$t1,[ ]+256 +[ ]+7c:[ ]+220101ac[ ]+ll.d[ ]+\$t0,[ ]+\$t1,[ ]+256 +[ ]+80:[ ]+230101ac[ ]+sc.d[ ]+\$t0,[ ]+\$t1,[ ]+256 +[ ]+84:[ ]+240101ac[ ]+ldptr.w[ ]+\$t0,[ ]+\$t1,[ ]+256 +[ ]+88:[ ]+250101ac[ ]+stptr.w[ ]+\$t0,[ ]+\$t1,[ ]+256 +[ ]+8c:[ ]+284401ac[ ]+ld.h[ ]+\$t0,[ ]+\$t1,[ ]+256 +[ ]+90:[ ]+288401ac[ ]+ld.w[ ]+\$t0,[ ]+\$t1,[ ]+256 +[ ]+94:[ ]+290401ac[ ]+st.b[ ]+\$t0,[ ]+\$t1,[ ]+256 +[ ]+98:[ ]+294401ac[ ]+st.h[ ]+\$t0,[ ]+\$t1,[ ]+256 +[ ]+9c:[ ]+298401ac[ ]+st.w[ ]+\$t0,[ ]+\$t1,[ ]+256 +[ ]+a0:[ ]+2a0401ac[ ]+ld.bu[ ]+\$t0,[ ]+\$t1,[ ]+256 +[ ]+a4:[ ]+2a4401ac[ ]+ld.hu[ ]+\$t0,[ ]+\$t1,[ ]+256 +[ ]+a8:[ ]+2a8401ac[ ]+ld.wu[ ]+\$t0,[ ]+\$t1,[ ]+256 +[ ]+ac:[ ]+2ac401a2[ ]+preld[ ]+0x2,[ ]+\$t1,[ ]+256 +[ ]+b0:[ ]+382c39a2[ ]+preldx[ ]+0x2,[ ]+\$t1,[ ]+\$t2 +[ ]+b4:[ ]+2b048d8a[ ]+fld.s[ ]+\$ft2,[ ]+\$t0,[ ]+291 +[ ]+b8:[ ]+2b448d8a[ ]+fst.s[ ]+\$ft2,[ ]+\$t0,[ ]+291 diff --git a/gas/testsuite/gas/loongarch/imm_ins_32.s b/gas/testsuite/gas/loongarch/imm_ins_32.s new file mode 100644 index 00000000..e105548e --- /dev/null +++ b/gas/testsuite/gas/loongarch/imm_ins_32.s @@ -0,0 +1,60 @@ +.equ a, 0x123 +.equ d, 2 +.equ e,0x100 + +li.w $r12, a + +alsl.w $r11,$r12,$r13,d +alsl.wu $r11,$r12,$r13,d +bytepick.w $r11,$r12,$r13,d + +break d +dbcl d +syscall d + +slli.w $r11,$r12,d +srli.w $r11,$r12,d +srai.w $r12,$r13,d + +bstrins.w $r12,$r13,d,d + +slti $r12,$r13,a +sltui $r12,$r13,a +addi.w $r12,$r13,a +andi $r12,$r13,d +ori $r12,$r13,d +xori $r12,$r13,d +lu12i.w $r12,a +pcaddi $r12,a +pcalau12i $r12,a +pcaddu12i $r12,a +pcaddu18i $r12,a + +csrrd $r12,a +csrwr $r12,a +csrxchg $r12,$r13,d +cacop d,$r13,d +lddir $r12,$r13,d +ldpte $r12,d + +invtlb d,$r13,$r14 + +ll.w $r12,$r13,e +sc.w $r12,$r13,e +ll.d $r12,$r13,e +sc.d $r12,$r13,e +ldptr.w $r12,$r13,e +stptr.w $r12,$r13,e +ld.h $r12,$r13,e +ld.w $r12,$r13,e +st.b $r12,$r13,e +st.h $r12,$r13,e +st.w $r12,$r13,e +ld.bu $r12,$r13,e +ld.hu $r12,$r13,e +ld.wu $r12,$r13,e +preld d,$r13,e +preldx d,$r13,$r14 + +fld.s $f10,$r12,a +fst.s $f10,$r12,a diff --git a/gas/testsuite/gas/loongarch/imm_ins_label-fail.d b/gas/testsuite/gas/loongarch/imm_ins_label-fail.d new file mode 100644 index 00000000..4301a007 --- /dev/null +++ b/gas/testsuite/gas/loongarch/imm_ins_label-fail.d @@ -0,0 +1,3 @@ +#as: +#source: imm_ins_label-fail.s +#error_output: imm_ins_label-fail.l diff --git a/gas/testsuite/gas/loongarch/imm_ins_label-fail.l b/gas/testsuite/gas/loongarch/imm_ins_label-fail.l new file mode 100644 index 00000000..e0fec2fe --- /dev/null +++ b/gas/testsuite/gas/loongarch/imm_ins_label-fail.l @@ -0,0 +1,3 @@ +.*Assembler messages: +.*Error: illegal operand: Label +.*Error: illegal operand: Label diff --git a/gas/testsuite/gas/loongarch/imm_ins_label-fail.s b/gas/testsuite/gas/loongarch/imm_ins_label-fail.s new file mode 100644 index 00000000..84b2d192 --- /dev/null +++ b/gas/testsuite/gas/loongarch/imm_ins_label-fail.s @@ -0,0 +1,3 @@ +Label: + li.w $r12, Label + addi.w $r12, $r13, Label diff --git a/gas/testsuite/gas/loongarch/imm_op.d b/gas/testsuite/gas/loongarch/imm_op.d index a017aaf5..3d4cba45 100644 --- a/gas/testsuite/gas/loongarch/imm_op.d +++ b/gas/testsuite/gas/loongarch/imm_op.d @@ -8,20 +8,20 @@ Disassembly of section .text: 00000000.* <.text>: [ ]+0:[ ]+020000a4 [ ]+slti[ ]+[ ]+\$a0, \$a1, 0 -[ ]+4:[ ]+021ffca4 [ ]+slti[ ]+[ ]+\$a0, \$a1, 2047\(0x7ff\) -[ ]+8:[ ]+022004a4 [ ]+slti[ ]+[ ]+\$a0, \$a1, -2047\(0x801\) +[ ]+4:[ ]+021ffca4 [ ]+slti[ ]+[ ]+\$a0, \$a1, 2047 +[ ]+8:[ ]+022004a4 [ ]+slti[ ]+[ ]+\$a0, \$a1, -2047 [ ]+c:[ ]+024000a4 [ ]+sltui[ ]+[ ]+\$a0, \$a1, 0 -[ ]+10:[ ]+025ffca4 [ ]+sltui[ ]+[ ]+\$a0, \$a1, 2047\(0x7ff\) -[ ]+14:[ ]+026004a4 [ ]+sltui[ ]+[ ]+\$a0, \$a1, -2047\(0x801\) +[ ]+10:[ ]+025ffca4 [ ]+sltui[ ]+[ ]+\$a0, \$a1, 2047 +[ ]+14:[ ]+026004a4 [ ]+sltui[ ]+[ ]+\$a0, \$a1, -2047 [ ]+18:[ ]+028000a4 [ ]+addi.w[ ]+[ ]+\$a0, \$a1, 0 -[ ]+1c:[ ]+029ffca4 [ ]+addi.w[ ]+[ ]+\$a0, \$a1, 2047\(0x7ff\) -[ ]+20:[ ]+02a004a4 [ ]+addi.w[ ]+[ ]+\$a0, \$a1, -2047\(0x801\) +[ ]+1c:[ ]+029ffca4 [ ]+addi.w[ ]+[ ]+\$a0, \$a1, 2047 +[ ]+20:[ ]+02a004a4 [ ]+addi.w[ ]+[ ]+\$a0, \$a1, -2047 [ ]+24:[ ]+02c000a4 [ ]+addi.d[ ]+[ ]+\$a0, \$a1, 0 -[ ]+28:[ ]+02dffca4 [ ]+addi.d[ ]+[ ]+\$a0, \$a1, 2047\(0x7ff\) -[ ]+2c:[ ]+02e004a4 [ ]+addi.d[ ]+[ ]+\$a0, \$a1, -2047\(0x801\) +[ ]+28:[ ]+02dffca4 [ ]+addi.d[ ]+[ ]+\$a0, \$a1, 2047 +[ ]+2c:[ ]+02e004a4 [ ]+addi.d[ ]+[ ]+\$a0, \$a1, -2047 [ ]+30:[ ]+030000a4 [ ]+lu52i.d[ ]+[ ]+\$a0, \$a1, 0 -[ ]+34:[ ]+031ffca4 [ ]+lu52i.d[ ]+[ ]+\$a0, \$a1, 2047\(0x7ff\) -[ ]+38:[ ]+032004a4 [ ]+lu52i.d[ ]+[ ]+\$a0, \$a1, -2047\(0x801\) +[ ]+34:[ ]+031ffca4 [ ]+lu52i.d[ ]+[ ]+\$a0, \$a1, 2047 +[ ]+38:[ ]+032004a4 [ ]+lu52i.d[ ]+[ ]+\$a0, \$a1, -2047 [ ]+3c:[ ]+034000a4 [ ]+andi[ ]+[ ]+\$a0, \$a1, 0x0 [ ]+40:[ ]+035ffca4 [ ]+andi[ ]+[ ]+\$a0, \$a1, 0x7ff [ ]+44:[ ]+038000a4 [ ]+ori[ ]+[ ]+\$a0, \$a1, 0x0 @@ -29,20 +29,20 @@ Disassembly of section .text: [ ]+4c:[ ]+03c000a4 [ ]+xori[ ]+[ ]+\$a0, \$a1, 0x0 [ ]+50:[ ]+03dffca4 [ ]+xori[ ]+[ ]+\$a0, \$a1, 0x7ff [ ]+54:[ ]+100000a4 [ ]+addu16i.d[ ]+[ ]+\$a0, \$a1, 0 -[ ]+58:[ ]+11fffca4 [ ]+addu16i.d[ ]+[ ]+\$a0, \$a1, 32767\(0x7fff\) -[ ]+5c:[ ]+120004a4 [ ]+addu16i.d[ ]+[ ]+\$a0, \$a1, -32767\(0x8001\) +[ ]+58:[ ]+11fffca4 [ ]+addu16i.d[ ]+[ ]+\$a0, \$a1, 32767 +[ ]+5c:[ ]+120004a4 [ ]+addu16i.d[ ]+[ ]+\$a0, \$a1, -32767 [ ]+60:[ ]+14000004 [ ]+lu12i.w[ ]+[ ]+\$a0, 0 -[ ]+64:[ ]+14ffffe4 [ ]+lu12i.w[ ]+[ ]+\$a0, 524287\(0x7ffff\) -[ ]+68:[ ]+17000024 [ ]+lu32i.d[ ]+[ ]+\$a0, -524287\(0x80001\) +[ ]+64:[ ]+14ffffe4 [ ]+lu12i.w[ ]+[ ]+\$a0, 524287 +[ ]+68:[ ]+17000024 [ ]+lu32i.d[ ]+[ ]+\$a0, -524287 [ ]+6c:[ ]+18000004 [ ]+pcaddi[ ]+[ ]+\$a0, 0 -[ ]+70:[ ]+18ffffe4 [ ]+pcaddi[ ]+[ ]+\$a0, 524287\(0x7ffff\) -[ ]+74:[ ]+19000024 [ ]+pcaddi[ ]+[ ]+\$a0, -524287\(0x80001\) +[ ]+70:[ ]+18ffffe4 [ ]+pcaddi[ ]+[ ]+\$a0, 524287 +[ ]+74:[ ]+19000024 [ ]+pcaddi[ ]+[ ]+\$a0, -524287 [ ]+78:[ ]+1a000004 [ ]+pcalau12i[ ]+[ ]+\$a0, 0 -[ ]+7c:[ ]+1affffe4 [ ]+pcalau12i[ ]+[ ]+\$a0, 524287\(0x7ffff\) -[ ]+80:[ ]+1b000024 [ ]+pcalau12i[ ]+[ ]+\$a0, -524287\(0x80001\) +[ ]+7c:[ ]+1affffe4 [ ]+pcalau12i[ ]+[ ]+\$a0, 524287 +[ ]+80:[ ]+1b000024 [ ]+pcalau12i[ ]+[ ]+\$a0, -524287 [ ]+84:[ ]+1c000004 [ ]+pcaddu12i[ ]+[ ]+\$a0, 0 -[ ]+88:[ ]+1cffffe4 [ ]+pcaddu12i[ ]+[ ]+\$a0, 524287\(0x7ffff\) -[ ]+8c:[ ]+1d000024 [ ]+pcaddu12i[ ]+[ ]+\$a0, -524287\(0x80001\) +[ ]+88:[ ]+1cffffe4 [ ]+pcaddu12i[ ]+[ ]+\$a0, 524287 +[ ]+8c:[ ]+1d000024 [ ]+pcaddu12i[ ]+[ ]+\$a0, -524287 [ ]+90:[ ]+1e000004 [ ]+pcaddu18i[ ]+[ ]+\$a0, 0 -[ ]+94:[ ]+1effffe4 [ ]+pcaddu18i[ ]+[ ]+\$a0, 524287\(0x7ffff\) -[ ]+98:[ ]+1f000024 [ ]+pcaddu18i[ ]+[ ]+\$a0, -524287\(0x80001\) +[ ]+94:[ ]+1effffe4 [ ]+pcaddu18i[ ]+[ ]+\$a0, 524287 +[ ]+98:[ ]+1f000024 [ ]+pcaddu18i[ ]+[ ]+\$a0, -524287 diff --git a/gas/testsuite/gas/loongarch/jmp_op.d b/gas/testsuite/gas/loongarch/jmp_op.d index fa939c78..cc544f11 100644 --- a/gas/testsuite/gas/loongarch/jmp_op.d +++ b/gas/testsuite/gas/loongarch/jmp_op.d @@ -6,25 +6,45 @@ Disassembly of section .text: -00000000.* <.text>: -[ ]+0:[ ]+03400000[ ]+[ ]+andi[ ]+\$zero, \$zero, 0x0 -[ ]+4:[ ]+63fffc04[ ]+[ ]+bgtz[ ]+\$a0, -4\(0x3fffc\)[ ]+# 0x0 -[ ]+8:[ ]+67fff880[ ]+[ ]+bgez[ ]+\$a0, -8\(0x3fff8\)[ ]+# 0x0 -[ ]+c:[ ]+67fff404[ ]+[ ]+blez[ ]+\$a0, -12\(0x3fff4\)[ ]+# 0x0 -[ ]+10:[ ]+43fff09f[ ]+[ ]+beqz[ ]+\$a0, -16\(0x7ffff0\)[ ]+# 0x0 -[ ]+14:[ ]+47ffec9f[ ]+[ ]+bnez[ ]+\$a0, -20\(0x7fffec\)[ ]+# 0x0 -[ ]+18:[ ]+4bffe81f[ ]+[ ]+bceqz[ ]+\$fcc0, -24\(0x7fffe8\)[ ]+# 0x0 -[ ]+1c:[ ]+4bffe51f[ ]+[ ]+bcnez[ ]+\$fcc0, -28\(0x7fffe4\)[ ]+# 0x0 -[ ]+20:[ ]+4c000080[ ]+[ ]+jirl[ ]+\$zero, \$a0, 0 -[ ]+24:[ ]+53ffdfff[ ]+[ ]+b[ ]+-36\(0xfffffdc\)[ ]+# 0x0 -[ ]+28:[ ]+57ffdbff[ ]+[ ]+bl[ ]+-40\(0xfffffd8\)[ ]+# 0x0 -[ ]+2c:[ ]+5bffd485[ ]+[ ]+beq[ ]+\$a0, \$a1, -44\(0x3ffd4\)[ ]+# 0x0 -[ ]+30:[ ]+5fffd085[ ]+[ ]+bne[ ]+\$a0, \$a1, -48\(0x3ffd0\)[ ]+# 0x0 -[ ]+34:[ ]+63ffcc85[ ]+[ ]+blt[ ]+\$a0, \$a1, -52\(0x3ffcc\)[ ]+# 0x0 -[ ]+38:[ ]+63ffc8a4[ ]+[ ]+blt[ ]+\$a1, \$a0, -56\(0x3ffc8\)[ ]+# 0x0 -[ ]+3c:[ ]+67ffc485[ ]+[ ]+bge[ ]+\$a0, \$a1, -60\(0x3ffc4\)[ ]+# 0x0 -[ ]+40:[ ]+67ffc0a4[ ]+[ ]+bge[ ]+\$a1, \$a0, -64\(0x3ffc0\)[ ]+# 0x0 -[ ]+44:[ ]+6bffbc85[ ]+[ ]+bltu[ ]+\$a0, \$a1, -68\(0x3ffbc\)[ ]+# 0x0 -[ ]+48:[ ]+6bffb8a4[ ]+[ ]+bltu[ ]+\$a1, \$a0, -72\(0x3ffb8\)[ ]+# 0x0 -[ ]+4c:[ ]+6fffb485[ ]+[ ]+bgeu[ ]+\$a0, \$a1, -76\(0x3ffb4\)[ ]+# 0x0 -[ ]+50:[ ]+6fffb0a4[ ]+[ ]+bgeu[ ]+\$a1, \$a0, -80\(0x3ffb0\)[ ]+# 0x0 +00000000.* <.L1>: +[ ]+0:[ ]+03400000[ ]+nop[ ]+ +[ ]+4:[ ]+63fffc04[ ]+bgtz[ ]+\$a0,[ ]+-4[ ]+#[ ]+0[ ]+<\.L1> +[ ]+4:[ ]+R_LARCH_B16[ ]+\.L1 +[ ]+8:[ ]+67fff880[ ]+bgez[ ]+\$a0,[ ]+-8[ ]+#[ ]+0[ ]+<\.L1> +[ ]+8:[ ]+R_LARCH_B16[ ]+\.L1 +[ ]+c:[ ]+67fff404[ ]+blez[ ]+\$a0,[ ]+-12[ ]+#[ ]+0[ ]+<\.L1> +[ ]+c:[ ]+R_LARCH_B16[ ]+\.L1 +[ ]+10:[ ]+43fff09f[ ]+beqz[ ]+\$a0,[ ]+-16[ ]+#[ ]+0[ ]+<\.L1> +[ ]+10:[ ]+R_LARCH_B21[ ]+\.L1 +[ ]+14:[ ]+47ffec9f[ ]+bnez[ ]+\$a0,[ ]+-20[ ]+#[ ]+0[ ]+<\.L1> +[ ]+14:[ ]+R_LARCH_B21[ ]+\.L1 +[ ]+18:[ ]+4bffe81f[ ]+bceqz[ ]+\$fcc0,[ ]+-24[ ]+#[ ]+0[ ]+<\.L1> +[ ]+18:[ ]+R_LARCH_B21[ ]+\.L1 +[ ]+1c:[ ]+4bffe51f[ ]+bcnez[ ]+\$fcc0,[ ]+-28[ ]+#[ ]+0[ ]+<\.L1> +[ ]+1c:[ ]+R_LARCH_B21[ ]+\.L1 +[ ]+20:[ ]+4c000080[ ]+jr[ ]+\$a0 +[ ]+24:[ ]+53ffdfff[ ]+b[ ]+-36[ ]+#[ ]+0[ ]+<\.L1> +[ ]+24:[ ]+R_LARCH_B26[ ]+\.L1 +[ ]+28:[ ]+57ffdbff[ ]+bl[ ]+-40[ ]+#[ ]+0[ ]+<\.L1> +[ ]+28:[ ]+R_LARCH_B26[ ]+\.L1 +[ ]+2c:[ ]+5bffd485[ ]+beq[ ]+\$a0,[ ]+\$a1,[ ]+-44[ ]+#[ ]+0[ ]+<\.L1> +[ ]+2c:[ ]+R_LARCH_B16[ ]+\.L1 +[ ]+30:[ ]+5fffd085[ ]+bne[ ]+\$a0,[ ]+\$a1,[ ]+-48[ ]+#[ ]+0[ ]+<\.L1> +[ ]+30:[ ]+R_LARCH_B16[ ]+\.L1 +[ ]+34:[ ]+63ffcc85[ ]+blt[ ]+\$a0,[ ]+\$a1,[ ]+-52[ ]+#[ ]+0[ ]+<\.L1> +[ ]+34:[ ]+R_LARCH_B16[ ]+\.L1 +[ ]+38:[ ]+63ffc8a4[ ]+blt[ ]+\$a1,[ ]+\$a0,[ ]+-56[ ]+#[ ]+0[ ]+<\.L1> +[ ]+38:[ ]+R_LARCH_B16[ ]+\.L1 +[ ]+3c:[ ]+67ffc485[ ]+bge[ ]+\$a0,[ ]+\$a1,[ ]+-60[ ]+#[ ]+0[ ]+<\.L1> +[ ]+3c:[ ]+R_LARCH_B16[ ]+\.L1 +[ ]+40:[ ]+67ffc0a4[ ]+bge[ ]+\$a1,[ ]+\$a0,[ ]+-64[ ]+#[ ]+0[ ]+<\.L1> +[ ]+40:[ ]+R_LARCH_B16[ ]+\.L1 +[ ]+44:[ ]+6bffbc85[ ]+bltu[ ]+\$a0,[ ]+\$a1,[ ]+-68[ ]+#[ ]+0[ ]+<\.L1> +[ ]+44:[ ]+R_LARCH_B16[ ]+\.L1 +[ ]+48:[ ]+6bffb8a4[ ]+bltu[ ]+\$a1,[ ]+\$a0,[ ]+-72[ ]+#[ ]+0[ ]+<\.L1> +[ ]+48:[ ]+R_LARCH_B16[ ]+\.L1 +[ ]+4c:[ ]+6fffb485[ ]+bgeu[ ]+\$a0,[ ]+\$a1,[ ]+-76[ ]+#[ ]+0[ ]+<\.L1> +[ ]+4c:[ ]+R_LARCH_B16[ ]+\.L1 +[ ]+50:[ ]+6fffb0a4[ ]+bgeu[ ]+\$a1,[ ]+\$a0,[ ]+-80[ ]+#[ ]+0[ ]+<\.L1> +[ ]+50:[ ]+R_LARCH_B16[ ]+\.L1 +[ ]+54:[ ]+4c000020[ ]+ret[ ]+ diff --git a/gas/testsuite/gas/loongarch/jmp_op.s b/gas/testsuite/gas/loongarch/jmp_op.s index 1deb165a..56f98678 100644 --- a/gas/testsuite/gas/loongarch/jmp_op.s +++ b/gas/testsuite/gas/loongarch/jmp_op.s @@ -20,3 +20,4 @@ bltu $r4,$r5,.L1 bgtu $r4,$r5,.L1 bgeu $r4,$r5,.L1 bleu $r4,$r5,.L1 +ret diff --git a/gas/testsuite/gas/loongarch/li.d b/gas/testsuite/gas/loongarch/li.d new file mode 100644 index 00000000..6f5bcd1d --- /dev/null +++ b/gas/testsuite/gas/loongarch/li.d @@ -0,0 +1,23 @@ +#as: +#objdump: -dr +#skip: loongarch32-*-* + +.*:[ ]+file format .* + + +Disassembly of section .text: + +00000000.* <_start>: +[ ]+0:[ ]+03803c06[ ]+li\.w[ ]+\$a2,[ ]+0xf +[ ]+4:[ ]+1a000005[ ]+pcalau12i[ ]+\$a1,[ ]+0 +[ ]+4:[ ]+R_LARCH_PCALA_HI20[ ]+msg +[ ]+4:[ ]+R_LARCH_RELAX[ ]+\*ABS\* +[ ]+8:[ ]+02c000a5[ ]+addi\.d[ ]+\$a1,[ ]+\$a1,[ ]+0 +[ ]+8:[ ]+R_LARCH_PCALA_LO12[ ]+msg +[ ]+8:[ ]+R_LARCH_RELAX[ ]+\*ABS\* +[ ]+c:[ ]+03800404[ ]+li\.w[ ]+\$a0,[ ]+0x1 +[ ]+10:[ ]+0381000b[ ]+li\.w[ ]+\$a7,[ ]+0x40 +[ ]+14:[ ]+002b0000[ ]+syscall[ ]+0x0 +[ ]+18:[ ]+00150004[ ]+move[ ]+\$a0,[ ]+\$zero +[ ]+1c:[ ]+0381740b[ ]+li\.w[ ]+\$a7,[ ]+0x5d +[ ]+20:[ ]+002b0000[ ]+syscall[ ]+0x0 diff --git a/gas/testsuite/gas/loongarch/li.s b/gas/testsuite/gas/loongarch/li.s new file mode 100644 index 00000000..e95a527f --- /dev/null +++ b/gas/testsuite/gas/loongarch/li.s @@ -0,0 +1,22 @@ +.equ EXIT_SUCCESS, 0 +.equ STDOUT, 1 +.equ SYS_exit, 93 +.equ SYS_write, 64 + +.section .rodata +msg: + .string "hello, world!\n" + len = . - msg + +.text + .globl _start +_start: + li.w $a2, len + la.local $a1, msg + li.w $a0, STDOUT + li.w $a7, SYS_write + syscall 0x0 + + li.w $a0, EXIT_SUCCESS + li.w $a7, SYS_exit + syscall 0x0 diff --git a/gas/testsuite/gas/loongarch/load_store_op.d b/gas/testsuite/gas/loongarch/load_store_op.d index fc15773c..e1b4dea1 100644 --- a/gas/testsuite/gas/loongarch/load_store_op.d +++ b/gas/testsuite/gas/loongarch/load_store_op.d @@ -8,69 +8,69 @@ Disassembly of section .text: 00000000.* <.text>: [ ]+0:[ ]+200000a4 [ ]+ll.w[ ]+[ ]+\$a0, \$a1, 0 -[ ]+4:[ ]+203ffca4 [ ]+ll.w[ ]+[ ]+\$a0, \$a1, 16380\(0x3ffc\) +[ ]+4:[ ]+203ffca4 [ ]+ll.w[ ]+[ ]+\$a0, \$a1, 16380 [ ]+8:[ ]+210000a4 [ ]+sc.w[ ]+[ ]+\$a0, \$a1, 0 -[ ]+c:[ ]+213ffca4 [ ]+sc.w[ ]+[ ]+\$a0, \$a1, 16380\(0x3ffc\) +[ ]+c:[ ]+213ffca4 [ ]+sc.w[ ]+[ ]+\$a0, \$a1, 16380 [ ]+10:[ ]+220000a4 [ ]+ll.d[ ]+[ ]+\$a0, \$a1, 0 -[ ]+14:[ ]+223ffca4 [ ]+ll.d[ ]+[ ]+\$a0, \$a1, 16380\(0x3ffc\) +[ ]+14:[ ]+223ffca4 [ ]+ll.d[ ]+[ ]+\$a0, \$a1, 16380 [ ]+18:[ ]+230000a4 [ ]+sc.d[ ]+[ ]+\$a0, \$a1, 0 -[ ]+1c:[ ]+233ffca4 [ ]+sc.d[ ]+[ ]+\$a0, \$a1, 16380\(0x3ffc\) +[ ]+1c:[ ]+233ffca4 [ ]+sc.d[ ]+[ ]+\$a0, \$a1, 16380 [ ]+20:[ ]+240000a4 [ ]+ldptr.w[ ]+[ ]+\$a0, \$a1, 0 -[ ]+24:[ ]+243ffca4 [ ]+ldptr.w[ ]+[ ]+\$a0, \$a1, 16380\(0x3ffc\) +[ ]+24:[ ]+243ffca4 [ ]+ldptr.w[ ]+[ ]+\$a0, \$a1, 16380 [ ]+28:[ ]+250000a4 [ ]+stptr.w[ ]+[ ]+\$a0, \$a1, 0 -[ ]+2c:[ ]+253ffca4 [ ]+stptr.w[ ]+[ ]+\$a0, \$a1, 16380\(0x3ffc\) +[ ]+2c:[ ]+253ffca4 [ ]+stptr.w[ ]+[ ]+\$a0, \$a1, 16380 [ ]+30:[ ]+260000a4 [ ]+ldptr.d[ ]+[ ]+\$a0, \$a1, 0 -[ ]+34:[ ]+263ffca4 [ ]+ldptr.d[ ]+[ ]+\$a0, \$a1, 16380\(0x3ffc\) +[ ]+34:[ ]+263ffca4 [ ]+ldptr.d[ ]+[ ]+\$a0, \$a1, 16380 [ ]+38:[ ]+270000a4 [ ]+stptr.d[ ]+[ ]+\$a0, \$a1, 0 -[ ]+3c:[ ]+273ffca4 [ ]+stptr.d[ ]+[ ]+\$a0, \$a1, 16380\(0x3ffc\) +[ ]+3c:[ ]+273ffca4 [ ]+stptr.d[ ]+[ ]+\$a0, \$a1, 16380 [ ]+40:[ ]+280000a4 [ ]+ld.b[ ]+[ ]+\$a0, \$a1, 0 -[ ]+44:[ ]+281ffca4 [ ]+ld.b[ ]+[ ]+\$a0, \$a1, 2047\(0x7ff\) -[ ]+48:[ ]+282004a4 [ ]+ld.b[ ]+[ ]+\$a0, \$a1, -2047\(0x801\) +[ ]+44:[ ]+281ffca4 [ ]+ld.b[ ]+[ ]+\$a0, \$a1, 2047 +[ ]+48:[ ]+282004a4 [ ]+ld.b[ ]+[ ]+\$a0, \$a1, -2047 [ ]+4c:[ ]+284000a4 [ ]+ld.h[ ]+[ ]+\$a0, \$a1, 0 -[ ]+50:[ ]+285ffca4 [ ]+ld.h[ ]+[ ]+\$a0, \$a1, 2047\(0x7ff\) -[ ]+54:[ ]+286004a4 [ ]+ld.h[ ]+[ ]+\$a0, \$a1, -2047\(0x801\) +[ ]+50:[ ]+285ffca4 [ ]+ld.h[ ]+[ ]+\$a0, \$a1, 2047 +[ ]+54:[ ]+286004a4 [ ]+ld.h[ ]+[ ]+\$a0, \$a1, -2047 [ ]+58:[ ]+288000a4 [ ]+ld.w[ ]+[ ]+\$a0, \$a1, 0 -[ ]+5c:[ ]+289ffca4 [ ]+ld.w[ ]+[ ]+\$a0, \$a1, 2047\(0x7ff\) -[ ]+60:[ ]+28a004a4 [ ]+ld.w[ ]+[ ]+\$a0, \$a1, -2047\(0x801\) +[ ]+5c:[ ]+289ffca4 [ ]+ld.w[ ]+[ ]+\$a0, \$a1, 2047 +[ ]+60:[ ]+28a004a4 [ ]+ld.w[ ]+[ ]+\$a0, \$a1, -2047 [ ]+64:[ ]+28c000a4 [ ]+ld.d[ ]+[ ]+\$a0, \$a1, 0 -[ ]+68:[ ]+28dffca4 [ ]+ld.d[ ]+[ ]+\$a0, \$a1, 2047\(0x7ff\) -[ ]+6c:[ ]+28e004a4 [ ]+ld.d[ ]+[ ]+\$a0, \$a1, -2047\(0x801\) +[ ]+68:[ ]+28dffca4 [ ]+ld.d[ ]+[ ]+\$a0, \$a1, 2047 +[ ]+6c:[ ]+28e004a4 [ ]+ld.d[ ]+[ ]+\$a0, \$a1, -2047 [ ]+70:[ ]+290000a4 [ ]+st.b[ ]+[ ]+\$a0, \$a1, 0 -[ ]+74:[ ]+291ffca4 [ ]+st.b[ ]+[ ]+\$a0, \$a1, 2047\(0x7ff\) -[ ]+78:[ ]+292004a4 [ ]+st.b[ ]+[ ]+\$a0, \$a1, -2047\(0x801\) +[ ]+74:[ ]+291ffca4 [ ]+st.b[ ]+[ ]+\$a0, \$a1, 2047 +[ ]+78:[ ]+292004a4 [ ]+st.b[ ]+[ ]+\$a0, \$a1, -2047 [ ]+7c:[ ]+294000a4 [ ]+st.h[ ]+[ ]+\$a0, \$a1, 0 -[ ]+80:[ ]+295ffca4 [ ]+st.h[ ]+[ ]+\$a0, \$a1, 2047\(0x7ff\) -[ ]+84:[ ]+296004a4 [ ]+st.h[ ]+[ ]+\$a0, \$a1, -2047\(0x801\) +[ ]+80:[ ]+295ffca4 [ ]+st.h[ ]+[ ]+\$a0, \$a1, 2047 +[ ]+84:[ ]+296004a4 [ ]+st.h[ ]+[ ]+\$a0, \$a1, -2047 [ ]+88:[ ]+298000a4 [ ]+st.w[ ]+[ ]+\$a0, \$a1, 0 -[ ]+8c:[ ]+299ffca4 [ ]+st.w[ ]+[ ]+\$a0, \$a1, 2047\(0x7ff\) -[ ]+90:[ ]+29a004a4 [ ]+st.w[ ]+[ ]+\$a0, \$a1, -2047\(0x801\) +[ ]+8c:[ ]+299ffca4 [ ]+st.w[ ]+[ ]+\$a0, \$a1, 2047 +[ ]+90:[ ]+29a004a4 [ ]+st.w[ ]+[ ]+\$a0, \$a1, -2047 [ ]+94:[ ]+29c000a4 [ ]+st.d[ ]+[ ]+\$a0, \$a1, 0 -[ ]+98:[ ]+29dffca4 [ ]+st.d[ ]+[ ]+\$a0, \$a1, 2047\(0x7ff\) -[ ]+9c:[ ]+29e004a4 [ ]+st.d[ ]+[ ]+\$a0, \$a1, -2047\(0x801\) +[ ]+98:[ ]+29dffca4 [ ]+st.d[ ]+[ ]+\$a0, \$a1, 2047 +[ ]+9c:[ ]+29e004a4 [ ]+st.d[ ]+[ ]+\$a0, \$a1, -2047 [ ]+a0:[ ]+2a0000a4 [ ]+ld.bu[ ]+[ ]+\$a0, \$a1, 0 -[ ]+a4:[ ]+2a1ffca4 [ ]+ld.bu[ ]+[ ]+\$a0, \$a1, 2047\(0x7ff\) -[ ]+a8:[ ]+2a2004a4 [ ]+ld.bu[ ]+[ ]+\$a0, \$a1, -2047\(0x801\) +[ ]+a4:[ ]+2a1ffca4 [ ]+ld.bu[ ]+[ ]+\$a0, \$a1, 2047 +[ ]+a8:[ ]+2a2004a4 [ ]+ld.bu[ ]+[ ]+\$a0, \$a1, -2047 [ ]+ac:[ ]+2a4000a4 [ ]+ld.hu[ ]+[ ]+\$a0, \$a1, 0 -[ ]+b0:[ ]+2a5ffca4 [ ]+ld.hu[ ]+[ ]+\$a0, \$a1, 2047\(0x7ff\) -[ ]+b4:[ ]+2a6004a4 [ ]+ld.hu[ ]+[ ]+\$a0, \$a1, -2047\(0x801\) +[ ]+b0:[ ]+2a5ffca4 [ ]+ld.hu[ ]+[ ]+\$a0, \$a1, 2047 +[ ]+b4:[ ]+2a6004a4 [ ]+ld.hu[ ]+[ ]+\$a0, \$a1, -2047 [ ]+b8:[ ]+2a8000a4 [ ]+ld.wu[ ]+[ ]+\$a0, \$a1, 0 -[ ]+bc:[ ]+2a9ffca4 [ ]+ld.wu[ ]+[ ]+\$a0, \$a1, 2047\(0x7ff\) -[ ]+c0:[ ]+2aa004a4 [ ]+ld.wu[ ]+[ ]+\$a0, \$a1, -2047\(0x801\) +[ ]+bc:[ ]+2a9ffca4 [ ]+ld.wu[ ]+[ ]+\$a0, \$a1, 2047 +[ ]+c0:[ ]+2aa004a4 [ ]+ld.wu[ ]+[ ]+\$a0, \$a1, -2047 [ ]+c4:[ ]+2ac000a0 [ ]+preld[ ]+[ ]+0x0, \$a1, 0 -[ ]+c8:[ ]+2adffcbf [ ]+preld[ ]+[ ]+0x1f, \$a1, 2047\(0x7ff\) -[ ]+cc:[ ]+2ae004bf [ ]+preld[ ]+[ ]+0x1f, \$a1, -2047\(0x801\) +[ ]+c8:[ ]+2adffcbf [ ]+preld[ ]+[ ]+0x1f, \$a1, 2047 +[ ]+cc:[ ]+2ae004bf [ ]+preld[ ]+[ ]+0x1f, \$a1, -2047 [ ]+d0:[ ]+2b0000a0 [ ]+fld.s[ ]+[ ]+\$fa0, \$a1, 0 -[ ]+d4:[ ]+2b1ffca0 [ ]+fld.s[ ]+[ ]+\$fa0, \$a1, 2047\(0x7ff\) -[ ]+d8:[ ]+2b2004a0 [ ]+fld.s[ ]+[ ]+\$fa0, \$a1, -2047\(0x801\) +[ ]+d4:[ ]+2b1ffca0 [ ]+fld.s[ ]+[ ]+\$fa0, \$a1, 2047 +[ ]+d8:[ ]+2b2004a0 [ ]+fld.s[ ]+[ ]+\$fa0, \$a1, -2047 [ ]+dc:[ ]+2b4000a0 [ ]+fst.s[ ]+[ ]+\$fa0, \$a1, 0 -[ ]+e0:[ ]+2b5ffca0 [ ]+fst.s[ ]+[ ]+\$fa0, \$a1, 2047\(0x7ff\) -[ ]+e4:[ ]+2b6004a0 [ ]+fst.s[ ]+[ ]+\$fa0, \$a1, -2047\(0x801\) +[ ]+e0:[ ]+2b5ffca0 [ ]+fst.s[ ]+[ ]+\$fa0, \$a1, 2047 +[ ]+e4:[ ]+2b6004a0 [ ]+fst.s[ ]+[ ]+\$fa0, \$a1, -2047 [ ]+e8:[ ]+2b8000a0 [ ]+fld.d[ ]+[ ]+\$fa0, \$a1, 0 -[ ]+ec:[ ]+2b9ffca0 [ ]+fld.d[ ]+[ ]+\$fa0, \$a1, 2047\(0x7ff\) -[ ]+f0:[ ]+2ba004a0 [ ]+fld.d[ ]+[ ]+\$fa0, \$a1, -2047\(0x801\) +[ ]+ec:[ ]+2b9ffca0 [ ]+fld.d[ ]+[ ]+\$fa0, \$a1, 2047 +[ ]+f0:[ ]+2ba004a0 [ ]+fld.d[ ]+[ ]+\$fa0, \$a1, -2047 [ ]+f4:[ ]+2bc000a0 [ ]+fst.d[ ]+[ ]+\$fa0, \$a1, 0 -[ ]+f8:[ ]+2bdffca0 [ ]+fst.d[ ]+[ ]+\$fa0, \$a1, 2047\(0x7ff\) -[ ]+fc:[ ]+2be004a0 [ ]+fst.d[ ]+[ ]+\$fa0, \$a1, -2047\(0x801\) +[ ]+f8:[ ]+2bdffca0 [ ]+fst.d[ ]+[ ]+\$fa0, \$a1, 2047 +[ ]+fc:[ ]+2be004a0 [ ]+fst.d[ ]+[ ]+\$fa0, \$a1, -2047 100:[ ]+380018a4 [ ]+ldx.b[ ]+[ ]+\$a0, \$a1, \$a2 104:[ ]+380418a4 [ ]+ldx.h[ ]+[ ]+\$a0, \$a1, \$a2 108:[ ]+380818a4 [ ]+ldx.w[ ]+[ ]+\$a0, \$a1, \$a2 diff --git a/gas/testsuite/gas/loongarch/loongarch.exp b/gas/testsuite/gas/loongarch/loongarch.exp index b8ee4b25..6d126fd4 100644 --- a/gas/testsuite/gas/loongarch/loongarch.exp +++ b/gas/testsuite/gas/loongarch/loongarch.exp @@ -1,5 +1,5 @@ # Expect script for LoongArch assembler tests. -# Copyright (C) 2021-2022 Free Software Foundation, Inc. +# Copyright (C) 2021-2023 Free Software Foundation, Inc. # # This file is part of the GNU Binutils. # diff --git a/gas/testsuite/gas/loongarch/lvz-lbt.d b/gas/testsuite/gas/loongarch/lvz-lbt.d new file mode 100644 index 00000000..f8970776 --- /dev/null +++ b/gas/testsuite/gas/loongarch/lvz-lbt.d @@ -0,0 +1,191 @@ +#as: +#objdump: -dr +#skip: loongarch32-*-* + +.*:[ ]+file format .* + + +Disassembly of section .text: + +00000000.* <.text>: +[ ]*0:[ ]*05000400[ ]*gcsrrd[ ]*\$zero,[ ]*0x1[ ]* +[ ]*4:[ ]*05000420[ ]*gcsrwr[ ]*\$zero,[ ]*0x1[ ]* +[ ]*8:[ ]*05000420[ ]*gcsrwr[ ]*\$zero,[ ]*0x1[ ]* +[ ]*c:[ ]*06482401[ ]*gtlbflush[ ]* +[ ]*10:[ ]*002b8001[ ]*hvcl[ ]*0x1[ ]* +[ ]*14:[ ]*00000820[ ]*movgr2scr[ ]*\$scr0,[ ]*\$ra[ ]* +[ ]*18:[ ]*00000c20[ ]*movscr2gr[ ]*\$zero,[ ]*\$scr1[ ]* +[ ]*1c:[ ]*48006600[ ]*jiscr0[ ]*100[ ]* +[ ]*20:[ ]*48006700[ ]*jiscr1[ ]*100[ ]* +[ ]*24:[ ]*00290420[ ]*addu12i\.w[ ]*\$zero,[ ]*\$ra,[ ]*1[ ]* +[ ]*28:[ ]*00298420[ ]*addu12i\.d[ ]*\$zero,[ ]*\$ra,[ ]*1[ ]* +[ ]*2c:[ ]*00300820[ ]*adc\.b[ ]*\$zero,[ ]*\$ra,[ ]*\$tp[ ]* +[ ]*30:[ ]*00308820[ ]*adc\.h[ ]*\$zero,[ ]*\$ra,[ ]*\$tp[ ]* +[ ]*34:[ ]*00310820[ ]*adc\.w[ ]*\$zero,[ ]*\$ra,[ ]*\$tp[ ]* +[ ]*38:[ ]*00318820[ ]*adc\.d[ ]*\$zero,[ ]*\$ra,[ ]*\$tp[ ]* +[ ]*3c:[ ]*00320820[ ]*sbc\.b[ ]*\$zero,[ ]*\$ra,[ ]*\$tp[ ]* +[ ]*40:[ ]*00328820[ ]*sbc\.h[ ]*\$zero,[ ]*\$ra,[ ]*\$tp[ ]* +[ ]*44:[ ]*00330820[ ]*sbc\.w[ ]*\$zero,[ ]*\$ra,[ ]*\$tp[ ]* +[ ]*48:[ ]*00338820[ ]*sbc\.d[ ]*\$zero,[ ]*\$ra,[ ]*\$tp[ ]* +[ ]*4c:[ ]*001a0820[ ]*rotr\.b[ ]*\$zero,[ ]*\$ra,[ ]*\$tp[ ]* +[ ]*50:[ ]*001a8820[ ]*rotr\.h[ ]*\$zero,[ ]*\$ra,[ ]*\$tp[ ]* +[ ]*54:[ ]*004c2420[ ]*rotri\.b[ ]*\$zero,[ ]*\$ra,[ ]*0x1[ ]* +[ ]*58:[ ]*004c4420[ ]*rotri\.h[ ]*\$zero,[ ]*\$ra,[ ]*0x1[ ]* +[ ]*5c:[ ]*00340820[ ]*rcr\.b[ ]*\$zero,[ ]*\$ra,[ ]*\$tp[ ]* +[ ]*60:[ ]*00348820[ ]*rcr\.h[ ]*\$zero,[ ]*\$ra,[ ]*\$tp[ ]* +[ ]*64:[ ]*00350820[ ]*rcr\.w[ ]*\$zero,[ ]*\$ra,[ ]*\$tp[ ]* +[ ]*68:[ ]*00358820[ ]*rcr\.d[ ]*\$zero,[ ]*\$ra,[ ]*\$tp[ ]* +[ ]*6c:[ ]*00502420[ ]*rcri\.b[ ]*\$zero,[ ]*\$ra,[ ]*0x1[ ]* +[ ]*70:[ ]*00504420[ ]*rcri\.h[ ]*\$zero,[ ]*\$ra,[ ]*0x1[ ]* +[ ]*74:[ ]*00508420[ ]*rcri\.w[ ]*\$zero,[ ]*\$ra,[ ]*0x1[ ]* +[ ]*78:[ ]*00510420[ ]*rcri\.d[ ]*\$zero,[ ]*\$ra,[ ]*0x1[ ]* +[ ]*7c:[ ]*0114e420[ ]*fcvt\.ud\.d[ ]*\$fa0,[ ]*\$fa1[ ]* +[ ]*80:[ ]*0114e020[ ]*fcvt\.ld\.d[ ]*\$fa0,[ ]*\$fa1[ ]* +[ ]*84:[ ]*01150820[ ]*fcvt\.d\.ld[ ]*\$fa0,[ ]*\$fa1,[ ]*\$fa2[ ]* +[ ]*88:[ ]*2e800420[ ]*ldl\.d[ ]*\$zero,[ ]*\$ra,[ ]*1[ ]* +[ ]*8c:[ ]*2e000420[ ]*ldl\.w[ ]*\$zero,[ ]*\$ra,[ ]*1[ ]* +[ ]*90:[ ]*2e400420[ ]*ldr\.w[ ]*\$zero,[ ]*\$ra,[ ]*1[ ]* +[ ]*94:[ ]*2ec00420[ ]*ldr\.d[ ]*\$zero,[ ]*\$ra,[ ]*1[ ]* +[ ]*98:[ ]*2f000420[ ]*stl\.w[ ]*\$zero,[ ]*\$ra,[ ]*1[ ]* +[ ]*9c:[ ]*2f800420[ ]*stl\.d[ ]*\$zero,[ ]*\$ra,[ ]*1[ ]* +[ ]*a0:[ ]*2f400420[ ]*str\.w[ ]*\$zero,[ ]*\$ra,[ ]*1[ ]* +[ ]*a4:[ ]*2fc00420[ ]*str\.d[ ]*\$zero,[ ]*\$ra,[ ]*1[ ]* +[ ]*a8:[ ]*003f040c[ ]*x86adc\.b[ ]*\$zero,[ ]*\$ra[ ]* +[ ]*ac:[ ]*003f040d[ ]*x86adc\.h[ ]*\$zero,[ ]*\$ra[ ]* +[ ]*b0:[ ]*003f040e[ ]*x86adc\.w[ ]*\$zero,[ ]*\$ra[ ]* +[ ]*b4:[ ]*003f040f[ ]*x86adc\.d[ ]*\$zero,[ ]*\$ra[ ]* +[ ]*b8:[ ]*003f0404[ ]*x86add\.b[ ]*\$zero,[ ]*\$ra[ ]* +[ ]*bc:[ ]*003f0405[ ]*x86add\.h[ ]*\$zero,[ ]*\$ra[ ]* +[ ]*c0:[ ]*003f0406[ ]*x86add\.w[ ]*\$zero,[ ]*\$ra[ ]* +[ ]*c4:[ ]*003f0407[ ]*x86add\.d[ ]*\$zero,[ ]*\$ra[ ]* +[ ]*c8:[ ]*003f0400[ ]*x86add\.wu[ ]*\$zero,[ ]*\$ra[ ]* +[ ]*cc:[ ]*003f0401[ ]*x86add\.du[ ]*\$zero,[ ]*\$ra[ ]* +[ ]*d0:[ ]*00008000[ ]*x86inc\.b[ ]*\$zero[ ]* +[ ]*d4:[ ]*00008001[ ]*x86inc\.h[ ]*\$zero[ ]* +[ ]*d8:[ ]*00008002[ ]*x86inc\.w[ ]*\$zero[ ]* +[ ]*dc:[ ]*00008003[ ]*x86inc\.d[ ]*\$zero[ ]* +[ ]*e0:[ ]*003f0410[ ]*x86sbc\.b[ ]*\$zero,[ ]*\$ra[ ]* +[ ]*e4:[ ]*003f0411[ ]*x86sbc\.h[ ]*\$zero,[ ]*\$ra[ ]* +[ ]*e8:[ ]*003f0412[ ]*x86sbc\.w[ ]*\$zero,[ ]*\$ra[ ]* +[ ]*ec:[ ]*003f0413[ ]*x86sbc\.d[ ]*\$zero,[ ]*\$ra[ ]* +[ ]*f0:[ ]*003f0408[ ]*x86sub\.b[ ]*\$zero,[ ]*\$ra[ ]* +[ ]*f4:[ ]*003f0409[ ]*x86sub\.h[ ]*\$zero,[ ]*\$ra[ ]* +[ ]*f8:[ ]*003f040a[ ]*x86sub\.w[ ]*\$zero,[ ]*\$ra[ ]* +[ ]*fc:[ ]*003f040b[ ]*x86sub\.d[ ]*\$zero,[ ]*\$ra[ ]* +[ ]*100:[ ]*003f0402[ ]*x86sub\.wu[ ]*\$zero,[ ]*\$ra[ ]* +[ ]*104:[ ]*003f0403[ ]*x86sub\.du[ ]*\$zero,[ ]*\$ra[ ]* +[ ]*108:[ ]*00008004[ ]*x86dec\.b[ ]*\$zero[ ]* +[ ]*10c:[ ]*00008005[ ]*x86dec\.h[ ]*\$zero[ ]* +[ ]*110:[ ]*00008006[ ]*x86dec\.w[ ]*\$zero[ ]* +[ ]*114:[ ]*00008007[ ]*x86dec\.d[ ]*\$zero[ ]* +[ ]*118:[ ]*003f8410[ ]*x86and\.b[ ]*\$zero,[ ]*\$ra[ ]* +[ ]*11c:[ ]*003f8411[ ]*x86and\.h[ ]*\$zero,[ ]*\$ra[ ]* +[ ]*120:[ ]*003f8412[ ]*x86and\.w[ ]*\$zero,[ ]*\$ra[ ]* +[ ]*124:[ ]*003f8413[ ]*x86and\.d[ ]*\$zero,[ ]*\$ra[ ]* +[ ]*128:[ ]*003f8414[ ]*x86or\.b[ ]*\$zero,[ ]*\$ra[ ]* +[ ]*12c:[ ]*003f8415[ ]*x86or\.h[ ]*\$zero,[ ]*\$ra[ ]* +[ ]*130:[ ]*003f8416[ ]*x86or\.w[ ]*\$zero,[ ]*\$ra[ ]* +[ ]*134:[ ]*003f8417[ ]*x86or\.d[ ]*\$zero,[ ]*\$ra[ ]* +[ ]*138:[ ]*003f8418[ ]*x86xor\.b[ ]*\$zero,[ ]*\$ra[ ]* +[ ]*13c:[ ]*003f8419[ ]*x86xor\.h[ ]*\$zero,[ ]*\$ra[ ]* +[ ]*140:[ ]*003f841a[ ]*x86xor\.w[ ]*\$zero,[ ]*\$ra[ ]* +[ ]*144:[ ]*003f841b[ ]*x86xor\.d[ ]*\$zero,[ ]*\$ra[ ]* +[ ]*148:[ ]*003e8400[ ]*x86mul\.b[ ]*\$zero,[ ]*\$ra[ ]* +[ ]*14c:[ ]*003e8401[ ]*x86mul\.h[ ]*\$zero,[ ]*\$ra[ ]* +[ ]*150:[ ]*003e8402[ ]*x86mul\.w[ ]*\$zero,[ ]*\$ra[ ]* +[ ]*154:[ ]*003e8403[ ]*x86mul\.d[ ]*\$zero,[ ]*\$ra[ ]* +[ ]*158:[ ]*003e8404[ ]*x86mul\.bu[ ]*\$zero,[ ]*\$ra[ ]* +[ ]*15c:[ ]*003e8405[ ]*x86mul\.hu[ ]*\$zero,[ ]*\$ra[ ]* +[ ]*160:[ ]*003e8406[ ]*x86mul\.wu[ ]*\$zero,[ ]*\$ra[ ]* +[ ]*164:[ ]*003e8407[ ]*x86mul\.du[ ]*\$zero,[ ]*\$ra[ ]* +[ ]*168:[ ]*003f840c[ ]*x86rcl\.b[ ]*\$zero,[ ]*\$ra[ ]* +[ ]*16c:[ ]*003f840d[ ]*x86rcl\.h[ ]*\$zero,[ ]*\$ra[ ]* +[ ]*170:[ ]*003f840e[ ]*x86rcl\.w[ ]*\$zero,[ ]*\$ra[ ]* +[ ]*174:[ ]*003f840f[ ]*x86rcl\.d[ ]*\$zero,[ ]*\$ra[ ]* +[ ]*178:[ ]*00542418[ ]*x86rcli\.b[ ]*\$zero,[ ]*0x1[ ]* +[ ]*17c:[ ]*00544419[ ]*x86rcli\.h[ ]*\$zero,[ ]*0x1[ ]* +[ ]*180:[ ]*0054841a[ ]*x86rcli\.w[ ]*\$zero,[ ]*0x1[ ]* +[ ]*184:[ ]*0055041b[ ]*x86rcli\.d[ ]*\$zero,[ ]*0x1[ ]* +[ ]*188:[ ]*003f8408[ ]*x86rcr\.b[ ]*\$zero,[ ]*\$ra[ ]* +[ ]*18c:[ ]*003f8409[ ]*x86rcr\.h[ ]*\$zero,[ ]*\$ra[ ]* +[ ]*190:[ ]*003f840a[ ]*x86rcr\.w[ ]*\$zero,[ ]*\$ra[ ]* +[ ]*194:[ ]*003f840b[ ]*x86rcr\.d[ ]*\$zero,[ ]*\$ra[ ]* +[ ]*198:[ ]*00542410[ ]*x86rcri\.b[ ]*\$zero,[ ]*0x1[ ]* +[ ]*19c:[ ]*00544411[ ]*x86rcri\.h[ ]*\$zero,[ ]*0x1[ ]* +[ ]*1a0:[ ]*00548412[ ]*x86rcri\.w[ ]*\$zero,[ ]*0x1[ ]* +[ ]*1a4:[ ]*00550413[ ]*x86rcri\.d[ ]*\$zero,[ ]*0x1[ ]* +[ ]*1a8:[ ]*003f8404[ ]*x86rotl\.b[ ]*\$zero,[ ]*\$ra[ ]* +[ ]*1ac:[ ]*003f8405[ ]*x86rotl\.h[ ]*\$zero,[ ]*\$ra[ ]* +[ ]*1b0:[ ]*003f8406[ ]*x86rotl\.w[ ]*\$zero,[ ]*\$ra[ ]* +[ ]*1b4:[ ]*003f8407[ ]*x86rotl\.d[ ]*\$zero,[ ]*\$ra[ ]* +[ ]*1b8:[ ]*00542414[ ]*x86rotli\.b[ ]*\$zero,[ ]*0x1[ ]* +[ ]*1bc:[ ]*00544415[ ]*x86rotli\.h[ ]*\$zero,[ ]*0x1[ ]* +[ ]*1c0:[ ]*00548416[ ]*x86rotli\.w[ ]*\$zero,[ ]*0x1[ ]* +[ ]*1c4:[ ]*00550417[ ]*x86rotli\.d[ ]*\$zero,[ ]*0x1[ ]* +[ ]*1c8:[ ]*003f8400[ ]*x86rotr\.b[ ]*\$zero,[ ]*\$ra[ ]* +[ ]*1cc:[ ]*003f8401[ ]*x86rotr\.h[ ]*\$zero,[ ]*\$ra[ ]* +[ ]*1d0:[ ]*003f8402[ ]*x86rotr\.d[ ]*\$zero,[ ]*\$ra[ ]* +[ ]*1d4:[ ]*003f8403[ ]*x86rotr\.w[ ]*\$zero,[ ]*\$ra[ ]* +[ ]*1d8:[ ]*0054240c[ ]*x86rotri\.b[ ]*\$zero,[ ]*0x1[ ]* +[ ]*1dc:[ ]*0054440d[ ]*x86rotri\.h[ ]*\$zero,[ ]*0x1[ ]* +[ ]*1e0:[ ]*0054840e[ ]*x86rotri\.w[ ]*\$zero,[ ]*0x1[ ]* +[ ]*1e4:[ ]*0055040f[ ]*x86rotri\.d[ ]*\$zero,[ ]*0x1[ ]* +[ ]*1e8:[ ]*003f0414[ ]*x86sll\.b[ ]*\$zero,[ ]*\$ra[ ]* +[ ]*1ec:[ ]*003f0415[ ]*x86sll\.h[ ]*\$zero,[ ]*\$ra[ ]* +[ ]*1f0:[ ]*003f0416[ ]*x86sll\.w[ ]*\$zero,[ ]*\$ra[ ]* +[ ]*1f4:[ ]*003f0417[ ]*x86sll\.d[ ]*\$zero,[ ]*\$ra[ ]* +[ ]*1f8:[ ]*00542400[ ]*x86slli\.b[ ]*\$zero,[ ]*0x1[ ]* +[ ]*1fc:[ ]*00544401[ ]*x86slli\.h[ ]*\$zero,[ ]*0x1[ ]* +[ ]*200:[ ]*00548402[ ]*x86slli\.w[ ]*\$zero,[ ]*0x1[ ]* +[ ]*204:[ ]*00550403[ ]*x86slli\.d[ ]*\$zero,[ ]*0x1[ ]* +[ ]*208:[ ]*003f0418[ ]*x86srl\.b[ ]*\$zero,[ ]*\$ra[ ]* +[ ]*20c:[ ]*003f0419[ ]*x86srl\.h[ ]*\$zero,[ ]*\$ra[ ]* +[ ]*210:[ ]*003f041a[ ]*x86srl\.w[ ]*\$zero,[ ]*\$ra[ ]* +[ ]*214:[ ]*003f041b[ ]*x86srl\.d[ ]*\$zero,[ ]*\$ra[ ]* +[ ]*218:[ ]*00542404[ ]*x86srli\.b[ ]*\$zero,[ ]*0x1[ ]* +[ ]*21c:[ ]*00544405[ ]*x86srli\.h[ ]*\$zero,[ ]*0x1[ ]* +[ ]*220:[ ]*00548406[ ]*x86srli\.w[ ]*\$zero,[ ]*0x1[ ]* +[ ]*224:[ ]*00550407[ ]*x86srli\.d[ ]*\$zero,[ ]*0x1[ ]* +[ ]*228:[ ]*003f041c[ ]*x86sra\.b[ ]*\$zero,[ ]*\$ra[ ]* +[ ]*22c:[ ]*003f041d[ ]*x86sra\.h[ ]*\$zero,[ ]*\$ra[ ]* +[ ]*230:[ ]*003f041e[ ]*x86sra\.w[ ]*\$zero,[ ]*\$ra[ ]* +[ ]*234:[ ]*003f041f[ ]*x86sra\.d[ ]*\$zero,[ ]*\$ra[ ]* +[ ]*238:[ ]*00542408[ ]*x86srai\.b[ ]*\$zero,[ ]*0x1[ ]* +[ ]*23c:[ ]*00544409[ ]*x86srai\.h[ ]*\$zero,[ ]*0x1[ ]* +[ ]*240:[ ]*0054840a[ ]*x86srai\.w[ ]*\$zero,[ ]*0x1[ ]* +[ ]*244:[ ]*0055040b[ ]*x86srai\.d[ ]*\$zero,[ ]*0x1[ ]* +[ ]*248:[ ]*00368400[ ]*setx86j[ ]*\$zero,[ ]*0x1[ ]* +[ ]*24c:[ ]*00007820[ ]*setx86loope[ ]*\$zero,[ ]*\$ra[ ]* +[ ]*250:[ ]*00007c20[ ]*setx86loopne[ ]*\$zero,[ ]*\$ra[ ]* +[ ]*254:[ ]*005c0400[ ]*x86mfflag[ ]*\$zero,[ ]*0x1[ ]* +[ ]*258:[ ]*005c0420[ ]*x86mtflag[ ]*\$zero,[ ]*0x1[ ]* +[ ]*25c:[ ]*00007400[ ]*x86mftop[ ]*\$zero[ ]* +[ ]*260:[ ]*00007020[ ]*x86mttop[ ]*0x1[ ]* +[ ]*264:[ ]*00008009[ ]*x86inctop[ ]* +[ ]*268:[ ]*00008029[ ]*x86dectop[ ]* +[ ]*26c:[ ]*00008008[ ]*x86settm[ ]* +[ ]*270:[ ]*00008028[ ]*x86clrtm[ ]* +[ ]*274:[ ]*00580420[ ]*x86settag[ ]*\$zero,[ ]*0x1,[ ]*0x1[ ]* +[ ]*278:[ ]*00370411[ ]*armadd\.w[ ]*\$zero,[ ]*\$ra,[ ]*0x1[ ]* +[ ]*27c:[ ]*00378411[ ]*armsub\.w[ ]*\$zero,[ ]*\$ra,[ ]*0x1[ ]* +[ ]*280:[ ]*00380411[ ]*armadc\.w[ ]*\$zero,[ ]*\$ra,[ ]*0x1[ ]* +[ ]*284:[ ]*00388411[ ]*armsbc\.w[ ]*\$zero,[ ]*\$ra,[ ]*0x1[ ]* +[ ]*288:[ ]*00390411[ ]*armand\.w[ ]*\$zero,[ ]*\$ra,[ ]*0x1[ ]* +[ ]*28c:[ ]*00398411[ ]*armor\.w[ ]*\$zero,[ ]*\$ra,[ ]*0x1[ ]* +[ ]*290:[ ]*003a0411[ ]*armxor\.w[ ]*\$zero,[ ]*\$ra,[ ]*0x1[ ]* +[ ]*294:[ ]*003fc41c[ ]*armnot\.w[ ]*\$zero,[ ]*0x1[ ]* +[ ]*298:[ ]*003a8411[ ]*armsll\.w[ ]*\$zero,[ ]*\$ra,[ ]*0x1[ ]* +[ ]*29c:[ ]*003b0411[ ]*armsrl\.w[ ]*\$zero,[ ]*\$ra,[ ]*0x1[ ]* +[ ]*2a0:[ ]*003b8411[ ]*armsra\.w[ ]*\$zero,[ ]*\$ra,[ ]*0x1[ ]* +[ ]*2a4:[ ]*003c0411[ ]*armrotr\.w[ ]*\$zero,[ ]*\$ra,[ ]*0x1[ ]* +[ ]*2a8:[ ]*003c8411[ ]*armslli\.w[ ]*\$zero,[ ]*0x1,[ ]*0x1[ ]* +[ ]*2ac:[ ]*003d0411[ ]*armsrli\.w[ ]*\$zero,[ ]*0x1,[ ]*0x1[ ]* +[ ]*2b0:[ ]*003d8411[ ]*armsrai\.w[ ]*\$zero,[ ]*0x1,[ ]*0x1[ ]* +[ ]*2b4:[ ]*003e0411[ ]*armrotri\.w[ ]*\$zero,[ ]*0x1,[ ]*0x1[ ]* +[ ]*2b8:[ ]*003fc41f[ ]*armrrx\.w[ ]*\$zero,[ ]*0x1[ ]* +[ ]*2bc:[ ]*00364420[ ]*armmove[ ]*\$zero,[ ]*\$ra,[ ]*0x1[ ]* +[ ]*2c0:[ ]*003fc41d[ ]*armmov\.w[ ]*\$zero,[ ]*0x1[ ]* +[ ]*2c4:[ ]*003fc41e[ ]*armmov\.d[ ]*\$zero,[ ]*0x1[ ]* +[ ]*2c8:[ ]*005c0440[ ]*armmfflag[ ]*\$zero,[ ]*0x1[ ]* +[ ]*2cc:[ ]*005c0460[ ]*armmtflag[ ]*\$zero,[ ]*0x1[ ]* +[ ]*2d0:[ ]*0036c400[ ]*setarmj[ ]*\$zero,[ ]*0x1[ ]* diff --git a/gas/testsuite/gas/loongarch/lvz-lbt.s b/gas/testsuite/gas/loongarch/lvz-lbt.s new file mode 100644 index 00000000..64469a43 --- /dev/null +++ b/gas/testsuite/gas/loongarch/lvz-lbt.s @@ -0,0 +1,181 @@ +gcsrrd $r0, 1 +gcsrwr $r0, 1 +gcsrxchg $r0, $r1, 1 +gtlbflush +hvcl 1 +movgr2scr $scr0, $r1 +movscr2gr $r0, $scr1 +jiscr0 100 +jiscr1 100 +addu12i.w $r0, $r1, 1 +addu12i.d $r0, $r1, 1 +adc.b $r0, $r1, $r2 +adc.h $r0, $r1, $r2 +adc.w $r0, $r1, $r2 +adc.d $r0, $r1, $r2 +sbc.b $r0, $r1, $r2 +sbc.h $r0, $r1, $r2 +sbc.w $r0, $r1, $r2 +sbc.d $r0, $r1, $r2 +rotr.b $r0, $r1, $r2 +rotr.h $r0, $r1, $r2 +rotri.b $r0, $r1, 1 +rotri.h $r0, $r1, 1 +rcr.b $r0, $r1, $r2 +rcr.h $r0, $r1, $r2 +rcr.w $r0, $r1, $r2 +rcr.d $r0, $r1, $r2 +rcri.b $r0, $r1, 1 +rcri.h $r0, $r1, 1 +rcri.w $r0, $r1, 1 +rcri.d $r0, $r1, 1 +fcvt.ud.d $f0, $f1 +fcvt.ld.d $f0, $f1 +fcvt.d.ld $f0, $f1, $f2 +ldl.d $r0, $r1, 1 +ldl.w $r0, $r1, 1 +ldr.w $r0, $r1, 1 +ldr.d $r0, $r1, 1 +stl.w $r0, $r1, 1 +stl.d $r0, $r1, 1 +str.w $r0, $r1, 1 +str.d $r0, $r1, 1 +x86adc.b $r0, $r1 +x86adc.h $r0, $r1 +x86adc.w $r0, $r1 +x86adc.d $r0, $r1 +x86add.b $r0, $r1 +x86add.h $r0, $r1 +x86add.w $r0, $r1 +x86add.d $r0, $r1 +x86add.wu $r0, $r1 +x86add.du $r0, $r1 +x86inc.b $r0 +x86inc.h $r0 +x86inc.w $r0 +x86inc.d $r0 +x86sbc.b $r0, $r1 +x86sbc.h $r0, $r1 +x86sbc.w $r0, $r1 +x86sbc.d $r0, $r1 +x86sub.b $r0, $r1 +x86sub.h $r0, $r1 +x86sub.w $r0, $r1 +x86sub.d $r0, $r1 +x86sub.wu $r0, $r1 +x86sub.du $r0, $r1 +x86dec.b $r0 +x86dec.h $r0 +x86dec.w $r0 +x86dec.d $r0 +x86and.b $r0, $r1 +x86and.h $r0, $r1 +x86and.w $r0, $r1 +x86and.d $r0, $r1 +x86or.b $r0, $r1 +x86or.h $r0, $r1 +x86or.w $r0, $r1 +x86or.d $r0, $r1 +x86xor.b $r0, $r1 +x86xor.h $r0, $r1 +x86xor.w $r0, $r1 +x86xor.d $r0, $r1 +x86mul.b $r0, $r1 +x86mul.h $r0, $r1 +x86mul.w $r0, $r1 +x86mul.d $r0, $r1 +x86mul.bu $r0, $r1 +x86mul.hu $r0, $r1 +x86mul.wu $r0, $r1 +x86mul.du $r0, $r1 +x86rcl.b $r0, $r1 +x86rcl.h $r0, $r1 +x86rcl.w $r0, $r1 +x86rcl.d $r0, $r1 +x86rcli.b $r0, 1 +x86rcli.h $r0, 1 +x86rcli.w $r0, 1 +x86rcli.d $r0, 1 +x86rcr.b $r0, $r1 +x86rcr.h $r0, $r1 +x86rcr.w $r0, $r1 +x86rcr.d $r0, $r1 +x86rcri.b $r0, 1 +x86rcri.h $r0, 1 +x86rcri.w $r0, 1 +x86rcri.d $r0, 1 +x86rotl.b $r0, $r1 +x86rotl.h $r0, $r1 +x86rotl.w $r0, $r1 +x86rotl.d $r0, $r1 +x86rotli.b $r0, 1 +x86rotli.h $r0, 1 +x86rotli.w $r0, 1 +x86rotli.d $r0, 1 +x86rotr.b $r0, $r1 +x86rotr.h $r0, $r1 +x86rotr.d $r0, $r1 +x86rotr.w $r0, $r1 +x86rotri.b $r0, 1 +x86rotri.h $r0, 1 +x86rotri.w $r0, 1 +x86rotri.d $r0, 1 +x86sll.b $r0, $r1 +x86sll.h $r0, $r1 +x86sll.w $r0, $r1 +x86sll.d $r0, $r1 +x86slli.b $r0, 1 +x86slli.h $r0, 1 +x86slli.w $r0, 1 +x86slli.d $r0, 1 +x86srl.b $r0, $r1 +x86srl.h $r0, $r1 +x86srl.w $r0, $r1 +x86srl.d $r0, $r1 +x86srli.b $r0, 1 +x86srli.h $r0, 1 +x86srli.w $r0, 1 +x86srli.d $r0, 1 +x86sra.b $r0, $r1 +x86sra.h $r0, $r1 +x86sra.w $r0, $r1 +x86sra.d $r0, $r1 +x86srai.b $r0, 1 +x86srai.h $r0, 1 +x86srai.w $r0, 1 +x86srai.d $r0, 1 +setx86j $r0, 1 +setx86loope $r0, $r1 +setx86loopne $r0, $r1 +x86mfflag $r0, 1 +x86mtflag $r0, 1 +x86mftop $r0 +x86mttop 1 +x86inctop +x86dectop +x86settm +x86clrtm +x86settag $r0, 1, 1 +armadd.w $r0, $r1, 1 +armsub.w $r0, $r1, 1 +armadc.w $r0, $r1, 1 +armsbc.w $r0, $r1, 1 +armand.w $r0, $r1, 1 +armor.w $r0, $r1, 1 +armxor.w $r0, $r1, 1 +armnot.w $r0, 1 +armsll.w $r0, $r1, 1 +armsrl.w $r0, $r1, 1 +armsra.w $r0, $r1, 1 +armrotr.w $r0, $r1, 1 +armslli.w $r0, 1, 1 +armsrli.w $r0, 1, 1 +armsrai.w $r0, 1, 1 +armrotri.w $r0, 1, 1 +armrrx.w $r0, 1 +armmove $r0, $r1, 1 +armmov.w $r0, 1 +armmov.d $r0, 1 +armmfflag $r0, 1 +armmtflag $r0, 1 +setarmj $r0, 1 diff --git a/gas/testsuite/gas/loongarch/macro_op.d b/gas/testsuite/gas/loongarch/macro_op.d index d264c4f2..32860864 100644 --- a/gas/testsuite/gas/loongarch/macro_op.d +++ b/gas/testsuite/gas/loongarch/macro_op.d @@ -9,51 +9,63 @@ Disassembly of section .text: 00000000.* <.text>: [ ]+0:[ ]+00150004[ ]+move[ ]+\$a0,[ ]+\$zero -[ ]+4:[ ]+02bffc04[ ]+addi.w[ ]+\$a0,[ ]+\$zero,[ ]+-1\(0xfff\) +[ ]+4:[ ]+02bffc04[ ]+li\.w[ ]+\$a0,[ ]+-1 [ ]+8:[ ]+00150004[ ]+move[ ]+\$a0,[ ]+\$zero -[ ]+c:[ ]+02bffc04[ ]+addi.w[ ]+\$a0,[ ]+\$zero,[ ]+-1\(0xfff\) +[ ]+c:[ ]+02bffc04[ ]+li\.w[ ]+\$a0,[ ]+-1 [ ]+10:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 -[ ]+10:[ ]+R_LARCH_GOT_PC_HI20[ ]+.L1 -[ ]+14:[ ]+28c00084[ ]+ld.d[ ]+\$a0,[ ]+\$a0,[ ]+0 -[ ]+14:[ ]+R_LARCH_GOT_PC_LO12[ ]+.L1 +[ ]+10:[ ]+R_LARCH_GOT_PC_HI20[ ]+\.L1 +[ ]+10:[ ]+R_LARCH_RELAX[ ]+\*ABS\* +[ ]+14:[ ]+28c00084[ ]+ld\.d[ ]+\$a0,[ ]+\$a0,[ ]+0 +[ ]+14:[ ]+R_LARCH_GOT_PC_LO12[ ]+\.L1 +[ ]+14:[ ]+R_LARCH_RELAX[ ]+\*ABS\* [ ]+18:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 -[ ]+18:[ ]+R_LARCH_GOT_PC_HI20[ ]+.L1 -[ ]+1c:[ ]+28c00084[ ]+ld.d[ ]+\$a0,[ ]+\$a0,[ ]+0 -[ ]+1c:[ ]+R_LARCH_GOT_PC_LO12[ ]+.L1 +[ ]+18:[ ]+R_LARCH_GOT_PC_HI20[ ]+\.L1 +[ ]+18:[ ]+R_LARCH_RELAX[ ]+\*ABS\* +[ ]+1c:[ ]+28c00084[ ]+ld\.d[ ]+\$a0,[ ]+\$a0,[ ]+0 +[ ]+1c:[ ]+R_LARCH_GOT_PC_LO12[ ]+\.L1 +[ ]+1c:[ ]+R_LARCH_RELAX[ ]+\*ABS\* [ ]+20:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 -[ ]+20:[ ]+R_LARCH_PCALA_HI20[ ]+.L1 -[ ]+24:[ ]+02c00084[ ]+addi.d[ ]+\$a0,[ ]+\$a0,[ ]+0 -[ ]+24:[ ]+R_LARCH_PCALA_LO12[ ]+.L1 -[ ]+28:[ ]+14000004[ ]+lu12i.w[ ]+\$a0,[ ]+0 +[ ]+20:[ ]+R_LARCH_PCALA_HI20[ ]+\.L1 +[ ]+20:[ ]+R_LARCH_RELAX[ ]+\*ABS\* +[ ]+24:[ ]+02c00084[ ]+addi\.d[ ]+\$a0,[ ]+\$a0,[ ]+0 +[ ]+24:[ ]+R_LARCH_PCALA_LO12[ ]+\.L1 +[ ]+24:[ ]+R_LARCH_RELAX[ ]+\*ABS\* +[ ]+28:[ ]+14000004[ ]+lu12i\.w[ ]+\$a0,[ ]+0 [ ]+28:[ ]+R_LARCH_MARK_LA[ ]+\*ABS\* -[ ]+28:[ ]+R_LARCH_ABS_HI20[ ]+.L1 +[ ]+28:[ ]+R_LARCH_ABS_HI20[ ]+\.L1 [ ]+2c:[ ]+03800084[ ]+ori[ ]+\$a0,[ ]+\$a0,[ ]+0x0 -[ ]+2c:[ ]+R_LARCH_ABS_LO12[ ]+.L1 -[ ]+30:[ ]+16000004[ ]+lu32i.d[ ]+\$a0,[ ]+0 -[ ]+30:[ ]+R_LARCH_ABS64_LO20[ ]+.L1 -[ ]+34:[ ]+03000084[ ]+lu52i.d[ ]+\$a0,[ ]+\$a0,[ ]+0 -[ ]+34:[ ]+R_LARCH_ABS64_HI12[ ]+.L1 +[ ]+2c:[ ]+R_LARCH_ABS_LO12[ ]+\.L1 +[ ]+30:[ ]+16000004[ ]+lu32i\.d[ ]+\$a0,[ ]+0 +[ ]+30:[ ]+R_LARCH_ABS64_LO20[ ]+\.L1 +[ ]+34:[ ]+03000084[ ]+lu52i\.d[ ]+\$a0,[ ]+\$a0,[ ]+0 +[ ]+34:[ ]+R_LARCH_ABS64_HI12[ ]+\.L1 [ ]+38:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 -[ ]+38:[ ]+R_LARCH_PCALA_HI20[ ]+.L1 -[ ]+3c:[ ]+02c00084[ ]+addi.d[ ]+\$a0,[ ]+\$a0,[ ]+0 -[ ]+3c:[ ]+R_LARCH_PCALA_LO12[ ]+.L1 +[ ]+38:[ ]+R_LARCH_PCALA_HI20[ ]+\.L1 +[ ]+38:[ ]+R_LARCH_RELAX[ ]+\*ABS\* +[ ]+3c:[ ]+02c00084[ ]+addi\.d[ ]+\$a0,[ ]+\$a0,[ ]+0 +[ ]+3c:[ ]+R_LARCH_PCALA_LO12[ ]+\.L1 +[ ]+3c:[ ]+R_LARCH_RELAX[ ]+\*ABS\* [ ]+40:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 -[ ]+40:[ ]+R_LARCH_GOT_PC_HI20[ ]+.L1 -[ ]+44:[ ]+28c00084[ ]+ld.d[ ]+\$a0,[ ]+\$a0,[ ]+0 -[ ]+44:[ ]+R_LARCH_GOT_PC_LO12[ ]+.L1 -[ ]+48:[ ]+14000004[ ]+lu12i.w[ ]+\$a0,[ ]+0 +[ ]+40:[ ]+R_LARCH_GOT_PC_HI20[ ]+\.L1 +[ ]+40:[ ]+R_LARCH_RELAX[ ]+\*ABS\* +[ ]+44:[ ]+28c00084[ ]+ld\.d[ ]+\$a0,[ ]+\$a0,[ ]+0 +[ ]+44:[ ]+R_LARCH_GOT_PC_LO12[ ]+\.L1 +[ ]+44:[ ]+R_LARCH_RELAX[ ]+\*ABS\* +[ ]+48:[ ]+14000004[ ]+lu12i\.w[ ]+\$a0,[ ]+0 [ ]+48:[ ]+R_LARCH_TLS_LE_HI20[ ]+TLS1 [ ]+4c:[ ]+03800084[ ]+ori[ ]+\$a0,[ ]+\$a0,[ ]+0x0 [ ]+4c:[ ]+R_LARCH_TLS_LE_LO12[ ]+TLS1 [ ]+50:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 [ ]+50:[ ]+R_LARCH_TLS_IE_PC_HI20[ ]+TLS1 -[ ]+54:[ ]+28c00084[ ]+ld.d[ ]+\$a0,[ ]+\$a0,[ ]+0 +[ ]+54:[ ]+28c00084[ ]+ld\.d[ ]+\$a0,[ ]+\$a0,[ ]+0 [ ]+54:[ ]+R_LARCH_TLS_IE_PC_LO12[ ]+TLS1 [ ]+58:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 [ ]+58:[ ]+R_LARCH_TLS_LD_PC_HI20[ ]+TLS1 -[ ]+5c:[ ]+02c00084[ ]+addi.d[ ]+\$a0,[ ]+\$a0,[ ]+0 +[ ]+5c:[ ]+02c00084[ ]+addi\.d[ ]+\$a0,[ ]+\$a0,[ ]+0 [ ]+5c:[ ]+R_LARCH_GOT_PC_LO12[ ]+TLS1 +[ ]+5c:[ ]+R_LARCH_RELAX[ ]+\*ABS\* [ ]+60:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 [ ]+60:[ ]+R_LARCH_TLS_GD_PC_HI20[ ]+TLS1 -[ ]+64:[ ]+02c00084[ ]+addi.d[ ]+\$a0,[ ]+\$a0,[ ]+0 +[ ]+64:[ ]+02c00084[ ]+addi\.d[ ]+\$a0,[ ]+\$a0,[ ]+0 [ ]+64:[ ]+R_LARCH_GOT_PC_LO12[ ]+TLS1 +[ ]+64:[ ]+R_LARCH_RELAX[ ]+\*ABS\* diff --git a/gas/testsuite/gas/loongarch/macro_op_32.d b/gas/testsuite/gas/loongarch/macro_op_32.d index 145d852b..188026a5 100644 --- a/gas/testsuite/gas/loongarch/macro_op_32.d +++ b/gas/testsuite/gas/loongarch/macro_op_32.d @@ -7,36 +7,46 @@ Disassembly of section .text: -00000000.* <.text>: +00000000.* <.L1>: [ ]+0:[ ]+00150004[ ]+move[ ]+\$a0,[ ]+\$zero -[ ]+4:[ ]+02bffc04[ ]+addi.w[ ]+\$a0,[ ]+\$zero,[ ]+-1\(0xfff\) +[ ]+4:[ ]+02bffc04[ ]+li\.w[ ]+\$a0,[ ]+-1 [ ]+8:[ ]+00150004[ ]+move[ ]+\$a0,[ ]+\$zero -[ ]+c:[ ]+02bffc04[ ]+addi.w[ ]+\$a0,[ ]+\$zero,[ ]+-1\(0xfff\) +[ ]+c:[ ]+02bffc04[ ]+li\.w[ ]+\$a0,[ ]+-1 [ ]+10:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 -[ ]+10:[ ]+R_LARCH_GOT_PC_HI20[ ]+.text +[ ]+10:[ ]+R_LARCH_GOT_PC_HI20[ ]+.L1 +[ ]+10:[ ]+R_LARCH_RELAX[ ]+\*ABS\* [ ]+14:[ ]+28800084[ ]+ld.w[ ]+\$a0,[ ]+\$a0,[ ]+0 -[ ]+14:[ ]+R_LARCH_GOT_PC_LO12[ ]+.text +[ ]+14:[ ]+R_LARCH_GOT_PC_LO12[ ]+.L1 +[ ]+14:[ ]+R_LARCH_RELAX[ ]+\*ABS\* [ ]+18:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 -[ ]+18:[ ]+R_LARCH_GOT_PC_HI20[ ]+.text +[ ]+18:[ ]+R_LARCH_GOT_PC_HI20[ ]+.L1 +[ ]+18:[ ]+R_LARCH_RELAX[ ]+\*ABS\* [ ]+1c:[ ]+28800084[ ]+ld.w[ ]+\$a0,[ ]+\$a0,[ ]+0 -[ ]+1c:[ ]+R_LARCH_GOT_PC_LO12[ ]+.text +[ ]+1c:[ ]+R_LARCH_GOT_PC_LO12[ ]+.L1 +[ ]+1c:[ ]+R_LARCH_RELAX[ ]+\*ABS\* [ ]+20:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 -[ ]+20:[ ]+R_LARCH_PCALA_HI20[ ]+.text +[ ]+20:[ ]+R_LARCH_PCALA_HI20[ ]+.L1 +[ ]+20:[ ]+R_LARCH_RELAX[ ]+\*ABS\* [ ]+24:[ ]+02800084[ ]+addi.w[ ]+\$a0,[ ]+\$a0,[ ]+0 -[ ]+24:[ ]+R_LARCH_PCALA_LO12[ ]+.text +[ ]+24:[ ]+R_LARCH_PCALA_LO12[ ]+.L1 +[ ]+24:[ ]+R_LARCH_RELAX[ ]+\*ABS\* [ ]+28:[ ]+14000004[ ]+lu12i.w[ ]+\$a0,[ ]+0 [ ]+28:[ ]+R_LARCH_MARK_LA[ ]+\*ABS\* -[ ]+28:[ ]+R_LARCH_ABS_HI20[ ]+.text +[ ]+28:[ ]+R_LARCH_ABS_HI20[ ]+.L1 [ ]+2c:[ ]+03800084[ ]+ori[ ]+\$a0,[ ]+\$a0,[ ]+0x0 -[ ]+2c:[ ]+R_LARCH_ABS_LO12[ ]+.text +[ ]+2c:[ ]+R_LARCH_ABS_LO12[ ]+.L1 [ ]+30:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 -[ ]+30:[ ]+R_LARCH_PCALA_HI20[ ]+.text +[ ]+30:[ ]+R_LARCH_PCALA_HI20[ ]+.L1 +[ ]+30:[ ]+R_LARCH_RELAX[ ]+\*ABS\* [ ]+34:[ ]+02800084[ ]+addi.w[ ]+\$a0,[ ]+\$a0,[ ]+0 -[ ]+34:[ ]+R_LARCH_PCALA_LO12[ ]+.text +[ ]+34:[ ]+R_LARCH_PCALA_LO12[ ]+.L1 +[ ]+34:[ ]+R_LARCH_RELAX[ ]+\*ABS\* [ ]+38:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 -[ ]+38:[ ]+R_LARCH_GOT_PC_HI20[ ]+.text +[ ]+38:[ ]+R_LARCH_GOT_PC_HI20[ ]+.L1 +[ ]+38:[ ]+R_LARCH_RELAX[ ]+\*ABS\* [ ]+3c:[ ]+28800084[ ]+ld.w[ ]+\$a0,[ ]+\$a0,[ ]+0 -[ ]+3c:[ ]+R_LARCH_GOT_PC_LO12[ ]+.text +[ ]+3c:[ ]+R_LARCH_GOT_PC_LO12[ ]+.L1 +[ ]+3c:[ ]+R_LARCH_RELAX[ ]+\*ABS\* [ ]+40:[ ]+14000004[ ]+lu12i.w[ ]+\$a0,[ ]+0 [ ]+40:[ ]+R_LARCH_TLS_LE_HI20[ ]+TLS1 [ ]+44:[ ]+03800084[ ]+ori[ ]+\$a0,[ ]+\$a0,[ ]+0x0 @@ -49,7 +59,9 @@ Disassembly of section .text: [ ]+50:[ ]+R_LARCH_TLS_LD_PC_HI20[ ]+TLS1 [ ]+54:[ ]+02800084[ ]+addi.w[ ]+\$a0,[ ]+\$a0,[ ]+0 [ ]+54:[ ]+R_LARCH_GOT_PC_LO12[ ]+TLS1 +[ ]+54:[ ]+R_LARCH_RELAX[ ]+\*ABS\* [ ]+58:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 [ ]+58:[ ]+R_LARCH_TLS_GD_PC_HI20[ ]+TLS1 [ ]+5c:[ ]+02800084[ ]+addi.w[ ]+\$a0,[ ]+\$a0,[ ]+0 [ ]+5c:[ ]+R_LARCH_GOT_PC_LO12[ ]+TLS1 +[ ]+5c:[ ]+R_LARCH_RELAX[ ]+\*ABS\* diff --git a/gas/testsuite/gas/loongarch/macro_op_large_abs.d b/gas/testsuite/gas/loongarch/macro_op_large_abs.d index c3214a85..0c49f68e 100644 --- a/gas/testsuite/gas/loongarch/macro_op_large_abs.d +++ b/gas/testsuite/gas/loongarch/macro_op_large_abs.d @@ -1,4 +1,4 @@ -#as: +#as: -mla-global-with-abs #objdump: -dr #skip: loongarch32-*-* @@ -7,71 +7,79 @@ Disassembly of section .text: -00000000.* <.text>: +00000000.* <.L1>: [ ]+0:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 -[ ]+0:[ ]+R_LARCH_PCALA_HI20[ ]+.text -[ ]+4:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0 -[ ]+4:[ ]+R_LARCH_PCALA_LO12[ ]+.text +[ ]+0:[ ]+R_LARCH_PCALA_HI20[ ]+.L1 +[ ]+0:[ ]+R_LARCH_RELAX[ ]+\*ABS\* +[ ]+4:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0 +[ ]+4:[ ]+R_LARCH_PCALA_LO12[ ]+.L1 +[ ]+4:[ ]+R_LARCH_RELAX[ ]+\*ABS\* [ ]+8:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0 -[ ]+8:[ ]+R_LARCH_PCALA64_LO20[ ]+.text +[ ]+8:[ ]+R_LARCH_PCALA64_LO20[ ]+.L1 [ ]+c:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1,[ ]+\$a1,[ ]+0 -[ ]+c:[ ]+R_LARCH_PCALA64_HI12[ ]+.text +[ ]+c:[ ]+R_LARCH_PCALA64_HI12[ ]+.L1 [ ]+10:[ ]+00109484[ ]+add.d[ ]+\$a0,[ ]+\$a0,[ ]+\$a1 -[ ]+14:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 -[ ]+14:[ ]+R_LARCH_GOT_PC_HI20[ ]+.text -[ ]+18:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0 -[ ]+18:[ ]+R_LARCH_GOT_PC_LO12[ ]+.text -[ ]+1c:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0 -[ ]+1c:[ ]+R_LARCH_GOT64_PC_LO20[ ]+.text -[ ]+20:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1,[ ]+\$a1,[ ]+0 -[ ]+20:[ ]+R_LARCH_GOT64_PC_HI12[ ]+.text -[ ]+24:[ ]+380c1484[ ]+ldx.d[ ]+\$a0,[ ]+\$a0,[ ]+\$a1 -[ ]+28:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 -[ ]+28:[ ]+R_LARCH_PCALA_HI20[ ]+.text -[ ]+2c:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0 -[ ]+2c:[ ]+R_LARCH_PCALA_LO12[ ]+.text -[ ]+30:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0 -[ ]+30:[ ]+R_LARCH_PCALA64_LO20[ ]+.text -[ ]+34:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1,[ ]+\$a1,[ ]+0 -[ ]+34:[ ]+R_LARCH_PCALA64_HI12[ ]+.text -[ ]+38:[ ]+00109484[ ]+add.d[ ]+\$a0,[ ]+\$a0,[ ]+\$a1 -[ ]+3c:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 -[ ]+3c:[ ]+R_LARCH_GOT_PC_HI20[ ]+.text -[ ]+40:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0 -[ ]+40:[ ]+R_LARCH_GOT_PC_LO12[ ]+.text -[ ]+44:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0 -[ ]+44:[ ]+R_LARCH_GOT64_PC_LO20[ ]+.text -[ ]+48:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1,[ ]+\$a1,[ ]+0 -[ ]+48:[ ]+R_LARCH_GOT64_PC_HI12[ ]+.text -[ ]+4c:[ ]+380c1484[ ]+ldx.d[ ]+\$a0,[ ]+\$a0,[ ]+\$a1 -[ ]+50:[ ]+14000004[ ]+lu12i.w[ ]+\$a0,[ ]+0 -[ ]+50:[ ]+R_LARCH_TLS_LE_HI20[ ]+TLS1 -[ ]+54:[ ]+03800084[ ]+ori[ ]+\$a0,[ ]+\$a0,[ ]+0x0 -[ ]+54:[ ]+R_LARCH_TLS_LE_LO12[ ]+TLS1 -[ ]+58:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 -[ ]+58:[ ]+R_LARCH_TLS_IE_PC_HI20[ ]+TLS1 -[ ]+5c:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0 -[ ]+5c:[ ]+R_LARCH_TLS_IE_PC_LO12[ ]+TLS1 -[ ]+60:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0 -[ ]+60:[ ]+R_LARCH_TLS_IE64_PC_LO20[ ]+TLS1 -[ ]+64:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1,[ ]+\$a1,[ ]+0 -[ ]+64:[ ]+R_LARCH_TLS_IE64_PC_HI12[ ]+TLS1 -[ ]+68:[ ]+380c1484[ ]+ldx.d[ ]+\$a0,[ ]+\$a0,[ ]+\$a1 -[ ]+6c:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 -[ ]+6c:[ ]+R_LARCH_TLS_LD_PC_HI20[ ]+TLS1 -[ ]+70:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0 -[ ]+70:[ ]+R_LARCH_GOT_PC_LO12[ ]+TLS1 -[ ]+74:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0 -[ ]+74:[ ]+R_LARCH_GOT64_PC_LO20[ ]+TLS1 -[ ]+78:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1,[ ]+\$a1,[ ]+0 -[ ]+78:[ ]+R_LARCH_GOT64_PC_HI12[ ]+TLS1 -[ ]+7c:[ ]+00109484[ ]+add.d[ ]+\$a0,[ ]+\$a0,[ ]+\$a1 -[ ]+80:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 -[ ]+80:[ ]+R_LARCH_TLS_GD_PC_HI20[ ]+TLS1 -[ ]+84:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0 -[ ]+84:[ ]+R_LARCH_GOT_PC_LO12[ ]+TLS1 -[ ]+88:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0 -[ ]+88:[ ]+R_LARCH_GOT64_PC_LO20[ ]+TLS1 -[ ]+8c:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1,[ ]+\$a1,[ ]+0 -[ ]+8c:[ ]+R_LARCH_GOT64_PC_HI12[ ]+TLS1 -[ ]+90:[ ]+00109484[ ]+add.d[ ]+\$a0,[ ]+\$a0,[ ]+\$a1 +[ ]+14:[ ]+14000004[ ]+lu12i.w[ ]+\$a0,[ ]+0 +[ ]+14:[ ]+R_LARCH_MARK_LA[ ]+\*ABS\* +[ ]+14:[ ]+R_LARCH_ABS_HI20[ ]+.L1 +[ ]+18:[ ]+03800084[ ]+ori[ ]+\$a0,[ ]+\$a0,[ ]+0x0 +[ ]+18:[ ]+R_LARCH_ABS_LO12[ ]+.L1 +[ ]+1c:[ ]+16000004[ ]+lu32i.d[ ]+\$a0,[ ]+0 +[ ]+1c:[ ]+R_LARCH_ABS64_LO20[ ]+.L1 +[ ]+20:[ ]+03000084[ ]+lu52i.d[ ]+\$a0,[ ]+\$a0,[ ]+0 +[ ]+20:[ ]+R_LARCH_ABS64_HI12[ ]+.L1 +[ ]+24:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 +[ ]+24:[ ]+R_LARCH_PCALA_HI20[ ]+.L1 +[ ]+24:[ ]+R_LARCH_RELAX[ ]+\*ABS\* +[ ]+28:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0 +[ ]+28:[ ]+R_LARCH_PCALA_LO12[ ]+.L1 +[ ]+28:[ ]+R_LARCH_RELAX[ ]+\*ABS\* +[ ]+2c:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0 +[ ]+2c:[ ]+R_LARCH_PCALA64_LO20[ ]+.L1 +[ ]+30:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1,[ ]+\$a1,[ ]+0 +[ ]+30:[ ]+R_LARCH_PCALA64_HI12[ ]+.L1 +[ ]+34:[ ]+00109484[ ]+add.d[ ]+\$a0,[ ]+\$a0,[ ]+\$a1 +[ ]+38:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 +[ ]+38:[ ]+R_LARCH_GOT_PC_HI20[ ]+.L1 +[ ]+38:[ ]+R_LARCH_RELAX[ ]+\*ABS\* +[ ]+3c:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0 +[ ]+3c:[ ]+R_LARCH_GOT_PC_LO12[ ]+.L1 +[ ]+3c:[ ]+R_LARCH_RELAX[ ]+\*ABS\* +[ ]+40:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0 +[ ]+40:[ ]+R_LARCH_GOT64_PC_LO20[ ]+.L1 +[ ]+44:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1,[ ]+\$a1,[ ]+0 +[ ]+44:[ ]+R_LARCH_GOT64_PC_HI12[ ]+.L1 +[ ]+48:[ ]+380c1484[ ]+ldx.d[ ]+\$a0,[ ]+\$a0,[ ]+\$a1 +[ ]+4c:[ ]+14000004[ ]+lu12i.w[ ]+\$a0,[ ]+0 +[ ]+4c:[ ]+R_LARCH_TLS_LE_HI20[ ]+TLS1 +[ ]+50:[ ]+03800084[ ]+ori[ ]+\$a0,[ ]+\$a0,[ ]+0x0 +[ ]+50:[ ]+R_LARCH_TLS_LE_LO12[ ]+TLS1 +[ ]+54:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 +[ ]+54:[ ]+R_LARCH_TLS_IE_PC_HI20[ ]+TLS1 +[ ]+58:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0 +[ ]+58:[ ]+R_LARCH_TLS_IE_PC_LO12[ ]+TLS1 +[ ]+5c:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0 +[ ]+5c:[ ]+R_LARCH_TLS_IE64_PC_LO20[ ]+TLS1 +[ ]+60:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1,[ ]+\$a1,[ ]+0 +[ ]+60:[ ]+R_LARCH_TLS_IE64_PC_HI12[ ]+TLS1 +[ ]+64:[ ]+380c1484[ ]+ldx.d[ ]+\$a0,[ ]+\$a0,[ ]+\$a1 +[ ]+68:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 +[ ]+68:[ ]+R_LARCH_TLS_LD_PC_HI20[ ]+TLS1 +[ ]+6c:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0 +[ ]+6c:[ ]+R_LARCH_GOT_PC_LO12[ ]+TLS1 +[ ]+6c:[ ]+R_LARCH_RELAX[ ]+\*ABS\* +[ ]+70:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0 +[ ]+70:[ ]+R_LARCH_GOT64_PC_LO20[ ]+TLS1 +[ ]+74:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1,[ ]+\$a1,[ ]+0 +[ ]+74:[ ]+R_LARCH_GOT64_PC_HI12[ ]+TLS1 +[ ]+78:[ ]+00109484[ ]+add.d[ ]+\$a0,[ ]+\$a0,[ ]+\$a1 +[ ]+7c:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 +[ ]+7c:[ ]+R_LARCH_TLS_GD_PC_HI20[ ]+TLS1 +[ ]+80:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0 +[ ]+80:[ ]+R_LARCH_GOT_PC_LO12[ ]+TLS1 +[ ]+80:[ ]+R_LARCH_RELAX[ ]+\*ABS\* +[ ]+84:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0 +[ ]+84:[ ]+R_LARCH_GOT64_PC_LO20[ ]+TLS1 +[ ]+88:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1,[ ]+\$a1,[ ]+0 +[ ]+88:[ ]+R_LARCH_GOT64_PC_HI12[ ]+TLS1 +[ ]+8c:[ ]+00109484[ ]+add.d[ ]+\$a0,[ ]+\$a0,[ ]+\$a1 diff --git a/gas/testsuite/gas/loongarch/macro_op_large_pc.d b/gas/testsuite/gas/loongarch/macro_op_large_pc.d index c3214a85..0c49f68e 100644 --- a/gas/testsuite/gas/loongarch/macro_op_large_pc.d +++ b/gas/testsuite/gas/loongarch/macro_op_large_pc.d @@ -1,4 +1,4 @@ -#as: +#as: -mla-global-with-abs #objdump: -dr #skip: loongarch32-*-* @@ -7,71 +7,79 @@ Disassembly of section .text: -00000000.* <.text>: +00000000.* <.L1>: [ ]+0:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 -[ ]+0:[ ]+R_LARCH_PCALA_HI20[ ]+.text -[ ]+4:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0 -[ ]+4:[ ]+R_LARCH_PCALA_LO12[ ]+.text +[ ]+0:[ ]+R_LARCH_PCALA_HI20[ ]+.L1 +[ ]+0:[ ]+R_LARCH_RELAX[ ]+\*ABS\* +[ ]+4:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0 +[ ]+4:[ ]+R_LARCH_PCALA_LO12[ ]+.L1 +[ ]+4:[ ]+R_LARCH_RELAX[ ]+\*ABS\* [ ]+8:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0 -[ ]+8:[ ]+R_LARCH_PCALA64_LO20[ ]+.text +[ ]+8:[ ]+R_LARCH_PCALA64_LO20[ ]+.L1 [ ]+c:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1,[ ]+\$a1,[ ]+0 -[ ]+c:[ ]+R_LARCH_PCALA64_HI12[ ]+.text +[ ]+c:[ ]+R_LARCH_PCALA64_HI12[ ]+.L1 [ ]+10:[ ]+00109484[ ]+add.d[ ]+\$a0,[ ]+\$a0,[ ]+\$a1 -[ ]+14:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 -[ ]+14:[ ]+R_LARCH_GOT_PC_HI20[ ]+.text -[ ]+18:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0 -[ ]+18:[ ]+R_LARCH_GOT_PC_LO12[ ]+.text -[ ]+1c:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0 -[ ]+1c:[ ]+R_LARCH_GOT64_PC_LO20[ ]+.text -[ ]+20:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1,[ ]+\$a1,[ ]+0 -[ ]+20:[ ]+R_LARCH_GOT64_PC_HI12[ ]+.text -[ ]+24:[ ]+380c1484[ ]+ldx.d[ ]+\$a0,[ ]+\$a0,[ ]+\$a1 -[ ]+28:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 -[ ]+28:[ ]+R_LARCH_PCALA_HI20[ ]+.text -[ ]+2c:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0 -[ ]+2c:[ ]+R_LARCH_PCALA_LO12[ ]+.text -[ ]+30:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0 -[ ]+30:[ ]+R_LARCH_PCALA64_LO20[ ]+.text -[ ]+34:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1,[ ]+\$a1,[ ]+0 -[ ]+34:[ ]+R_LARCH_PCALA64_HI12[ ]+.text -[ ]+38:[ ]+00109484[ ]+add.d[ ]+\$a0,[ ]+\$a0,[ ]+\$a1 -[ ]+3c:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 -[ ]+3c:[ ]+R_LARCH_GOT_PC_HI20[ ]+.text -[ ]+40:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0 -[ ]+40:[ ]+R_LARCH_GOT_PC_LO12[ ]+.text -[ ]+44:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0 -[ ]+44:[ ]+R_LARCH_GOT64_PC_LO20[ ]+.text -[ ]+48:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1,[ ]+\$a1,[ ]+0 -[ ]+48:[ ]+R_LARCH_GOT64_PC_HI12[ ]+.text -[ ]+4c:[ ]+380c1484[ ]+ldx.d[ ]+\$a0,[ ]+\$a0,[ ]+\$a1 -[ ]+50:[ ]+14000004[ ]+lu12i.w[ ]+\$a0,[ ]+0 -[ ]+50:[ ]+R_LARCH_TLS_LE_HI20[ ]+TLS1 -[ ]+54:[ ]+03800084[ ]+ori[ ]+\$a0,[ ]+\$a0,[ ]+0x0 -[ ]+54:[ ]+R_LARCH_TLS_LE_LO12[ ]+TLS1 -[ ]+58:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 -[ ]+58:[ ]+R_LARCH_TLS_IE_PC_HI20[ ]+TLS1 -[ ]+5c:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0 -[ ]+5c:[ ]+R_LARCH_TLS_IE_PC_LO12[ ]+TLS1 -[ ]+60:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0 -[ ]+60:[ ]+R_LARCH_TLS_IE64_PC_LO20[ ]+TLS1 -[ ]+64:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1,[ ]+\$a1,[ ]+0 -[ ]+64:[ ]+R_LARCH_TLS_IE64_PC_HI12[ ]+TLS1 -[ ]+68:[ ]+380c1484[ ]+ldx.d[ ]+\$a0,[ ]+\$a0,[ ]+\$a1 -[ ]+6c:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 -[ ]+6c:[ ]+R_LARCH_TLS_LD_PC_HI20[ ]+TLS1 -[ ]+70:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0 -[ ]+70:[ ]+R_LARCH_GOT_PC_LO12[ ]+TLS1 -[ ]+74:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0 -[ ]+74:[ ]+R_LARCH_GOT64_PC_LO20[ ]+TLS1 -[ ]+78:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1,[ ]+\$a1,[ ]+0 -[ ]+78:[ ]+R_LARCH_GOT64_PC_HI12[ ]+TLS1 -[ ]+7c:[ ]+00109484[ ]+add.d[ ]+\$a0,[ ]+\$a0,[ ]+\$a1 -[ ]+80:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 -[ ]+80:[ ]+R_LARCH_TLS_GD_PC_HI20[ ]+TLS1 -[ ]+84:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0 -[ ]+84:[ ]+R_LARCH_GOT_PC_LO12[ ]+TLS1 -[ ]+88:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0 -[ ]+88:[ ]+R_LARCH_GOT64_PC_LO20[ ]+TLS1 -[ ]+8c:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1,[ ]+\$a1,[ ]+0 -[ ]+8c:[ ]+R_LARCH_GOT64_PC_HI12[ ]+TLS1 -[ ]+90:[ ]+00109484[ ]+add.d[ ]+\$a0,[ ]+\$a0,[ ]+\$a1 +[ ]+14:[ ]+14000004[ ]+lu12i.w[ ]+\$a0,[ ]+0 +[ ]+14:[ ]+R_LARCH_MARK_LA[ ]+\*ABS\* +[ ]+14:[ ]+R_LARCH_ABS_HI20[ ]+.L1 +[ ]+18:[ ]+03800084[ ]+ori[ ]+\$a0,[ ]+\$a0,[ ]+0x0 +[ ]+18:[ ]+R_LARCH_ABS_LO12[ ]+.L1 +[ ]+1c:[ ]+16000004[ ]+lu32i.d[ ]+\$a0,[ ]+0 +[ ]+1c:[ ]+R_LARCH_ABS64_LO20[ ]+.L1 +[ ]+20:[ ]+03000084[ ]+lu52i.d[ ]+\$a0,[ ]+\$a0,[ ]+0 +[ ]+20:[ ]+R_LARCH_ABS64_HI12[ ]+.L1 +[ ]+24:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 +[ ]+24:[ ]+R_LARCH_PCALA_HI20[ ]+.L1 +[ ]+24:[ ]+R_LARCH_RELAX[ ]+\*ABS\* +[ ]+28:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0 +[ ]+28:[ ]+R_LARCH_PCALA_LO12[ ]+.L1 +[ ]+28:[ ]+R_LARCH_RELAX[ ]+\*ABS\* +[ ]+2c:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0 +[ ]+2c:[ ]+R_LARCH_PCALA64_LO20[ ]+.L1 +[ ]+30:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1,[ ]+\$a1,[ ]+0 +[ ]+30:[ ]+R_LARCH_PCALA64_HI12[ ]+.L1 +[ ]+34:[ ]+00109484[ ]+add.d[ ]+\$a0,[ ]+\$a0,[ ]+\$a1 +[ ]+38:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 +[ ]+38:[ ]+R_LARCH_GOT_PC_HI20[ ]+.L1 +[ ]+38:[ ]+R_LARCH_RELAX[ ]+\*ABS\* +[ ]+3c:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0 +[ ]+3c:[ ]+R_LARCH_GOT_PC_LO12[ ]+.L1 +[ ]+3c:[ ]+R_LARCH_RELAX[ ]+\*ABS\* +[ ]+40:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0 +[ ]+40:[ ]+R_LARCH_GOT64_PC_LO20[ ]+.L1 +[ ]+44:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1,[ ]+\$a1,[ ]+0 +[ ]+44:[ ]+R_LARCH_GOT64_PC_HI12[ ]+.L1 +[ ]+48:[ ]+380c1484[ ]+ldx.d[ ]+\$a0,[ ]+\$a0,[ ]+\$a1 +[ ]+4c:[ ]+14000004[ ]+lu12i.w[ ]+\$a0,[ ]+0 +[ ]+4c:[ ]+R_LARCH_TLS_LE_HI20[ ]+TLS1 +[ ]+50:[ ]+03800084[ ]+ori[ ]+\$a0,[ ]+\$a0,[ ]+0x0 +[ ]+50:[ ]+R_LARCH_TLS_LE_LO12[ ]+TLS1 +[ ]+54:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 +[ ]+54:[ ]+R_LARCH_TLS_IE_PC_HI20[ ]+TLS1 +[ ]+58:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0 +[ ]+58:[ ]+R_LARCH_TLS_IE_PC_LO12[ ]+TLS1 +[ ]+5c:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0 +[ ]+5c:[ ]+R_LARCH_TLS_IE64_PC_LO20[ ]+TLS1 +[ ]+60:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1,[ ]+\$a1,[ ]+0 +[ ]+60:[ ]+R_LARCH_TLS_IE64_PC_HI12[ ]+TLS1 +[ ]+64:[ ]+380c1484[ ]+ldx.d[ ]+\$a0,[ ]+\$a0,[ ]+\$a1 +[ ]+68:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 +[ ]+68:[ ]+R_LARCH_TLS_LD_PC_HI20[ ]+TLS1 +[ ]+6c:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0 +[ ]+6c:[ ]+R_LARCH_GOT_PC_LO12[ ]+TLS1 +[ ]+6c:[ ]+R_LARCH_RELAX[ ]+\*ABS\* +[ ]+70:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0 +[ ]+70:[ ]+R_LARCH_GOT64_PC_LO20[ ]+TLS1 +[ ]+74:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1,[ ]+\$a1,[ ]+0 +[ ]+74:[ ]+R_LARCH_GOT64_PC_HI12[ ]+TLS1 +[ ]+78:[ ]+00109484[ ]+add.d[ ]+\$a0,[ ]+\$a0,[ ]+\$a1 +[ ]+7c:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 +[ ]+7c:[ ]+R_LARCH_TLS_GD_PC_HI20[ ]+TLS1 +[ ]+80:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0 +[ ]+80:[ ]+R_LARCH_GOT_PC_LO12[ ]+TLS1 +[ ]+80:[ ]+R_LARCH_RELAX[ ]+\*ABS\* +[ ]+84:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0 +[ ]+84:[ ]+R_LARCH_GOT64_PC_LO20[ ]+TLS1 +[ ]+88:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1,[ ]+\$a1,[ ]+0 +[ ]+88:[ ]+R_LARCH_GOT64_PC_HI12[ ]+TLS1 +[ ]+8c:[ ]+00109484[ ]+add.d[ ]+\$a0,[ ]+\$a0,[ ]+\$a1 diff --git a/gas/testsuite/gas/loongarch/nop.d b/gas/testsuite/gas/loongarch/nop.d index 4cdcc5ce..222456e8 100644 --- a/gas/testsuite/gas/loongarch/nop.d +++ b/gas/testsuite/gas/loongarch/nop.d @@ -7,4 +7,4 @@ Disassembly of section .text: 0+000 <target>: -[ ]+0:[ ]+03400000[ ]+andi[ ]+\$zero, \$zero, 0x0 +[ ]+0:[ ]+03400000[ ]+nop[ ]+ diff --git a/gas/testsuite/gas/loongarch/pcrel_norelax.d b/gas/testsuite/gas/loongarch/pcrel_norelax.d new file mode 100644 index 00000000..842c8d48 --- /dev/null +++ b/gas/testsuite/gas/loongarch/pcrel_norelax.d @@ -0,0 +1,56 @@ +#as: -mno-relax +#objdump: -Dr + +.*:[ ]+file format .* + + +Disassembly of section .text: + +00000000.* <.L1>: +[ ]+... +[ ]+0:[ ]+R_LARCH_32_PCREL[ ]+.L3 +[ ]+4:[ ]+R_LARCH_32_PCREL[ ]+.L3\+0x4 + +0*00000008[ ]+<.L2>: +[ ]+... +[ ]+8:[ ]+R_LARCH_64_PCREL[ ]+.L3 +[ ]+10:[ ]+R_LARCH_64_PCREL[ ]+.L3\+0x8 + +Disassembly[ ]+of[ ]+section[ ]+sx: + +0*00000000[ ]+<.L3>: +[ ]+0:[ ]+fffffff4[ ]+.word[ ]+0xfffffff4 +[ ]+4:[ ]+fffffff4[ ]+.word[ ]+0xfffffff4 +[ ]+8:[ ]+ffffffff[ ]+.word[ ]+0xffffffff + +0*0000000c[ ]+<.L4>: +[ ]+... +[ ]+c:[ ]+R_LARCH_ADD32[ ]+.L4 +[ ]+c:[ ]+R_LARCH_SUB32[ ]+.L5 +[ ]+10:[ ]+R_LARCH_ADD64[ ]+.L4 +[ ]+10:[ ]+R_LARCH_SUB64[ ]+.L5 + +Disassembly[ ]+of[ ]+section[ ]+sy: + +0*00000000[ ]+<.L5>: +[ ]+... +[ ]+0:[ ]+R_LARCH_32_PCREL[ ]+.L1 +[ ]+4:[ ]+R_LARCH_32_PCREL[ ]+.L2\+0x4 +[ ]+8:[ ]+R_LARCH_64_PCREL[ ]+.L1\+0x8 +[ ]+10:[ ]+R_LARCH_64_PCREL[ ]+.L2\+0x10 + +Disassembly[ ]+of[ ]+section[ ]+sz: + +0*00000000[ ]+<sz>: +[ ]+0:[ ]+fffffff8[ ]+.word[ ]+0xfffffff8 +[ ]+4:[ ]+fffffff4[ ]+.word[ ]+0xfffffff4 +[ ]+8:[ ]+00000000[ ]+.word[ ]+0x00000000 +[ ]+8:[ ]+R_LARCH_ADD32[ ]+.L2 +[ ]+8:[ ]+R_LARCH_SUB32[ ]+.L3 +[ ]+c:[ ]+fffffff8[ ]+.word[ ]+0xfffffff8 +[ ]+10:[ ]+ffffffff[ ]+.word[ ]+0xffffffff +[ ]+14:[ ]+fffffff4[ ]+.word[ ]+0xfffffff4 +[ ]+18:[ ]+ffffffff[ ]+.word[ ]+0xffffffff +[ ]+... +[ ]+1c:[ ]+R_LARCH_ADD64[ ]+.L2 +[ ]+1c:[ ]+R_LARCH_SUB64[ ]+.L3 diff --git a/gas/testsuite/gas/loongarch/pcrel_norelax.s b/gas/testsuite/gas/loongarch/pcrel_norelax.s new file mode 100644 index 00000000..09527f14 --- /dev/null +++ b/gas/testsuite/gas/loongarch/pcrel_norelax.s @@ -0,0 +1,42 @@ + .section .text +.L1: + # 32_pcrel + .4byte .L3-.L1 + .4byte .L3-.L1 +.L2: + # 64_pcrel + .8byte .L3-.L2 + .8byte .L3-.L2 + + .section sx +.L3: + # no relocation + .4byte .L3-.L4 + .8byte .L3-.L4 +.L4: + # add32+sub32 + .4byte .L4-.L5 + # add64+sub64 + .8byte .L4-.L5 + + .section sy +.L5: + # 32_pcrel + .4byte .L1-.L5 + .4byte .L2-.L5 + # 64_pcrel + .8byte .L1-.L5 + .8byte .L2-.L5 + + .section sz + # no relocation + .4byte .L1-.L2 + .4byte .L3-.L4 + # add32+sub32 + .4byte .L2-.L3 + + # no relocation + .8byte .L1-.L2 + .8byte .L3-.L4 + # add64+sub64 + .8byte .L2-.L3 diff --git a/gas/testsuite/gas/loongarch/pcrel_relax.d b/gas/testsuite/gas/loongarch/pcrel_relax.d new file mode 100644 index 00000000..d6f87525 --- /dev/null +++ b/gas/testsuite/gas/loongarch/pcrel_relax.d @@ -0,0 +1,60 @@ +#as: +#objdump: -Dr + +.*:[ ]+file format .* + + +Disassembly of section .text: + +00000000.* <.L1>: +[ ]+... +[ ]+0:[ ]+R_LARCH_32_PCREL[ ]+.L3 +[ ]+4:[ ]+R_LARCH_ADD32[ ]+.L3 +[ ]+4:[ ]+R_LARCH_SUB32[ ]+.L1 + +0*00000008[ ]+<.L2>: +[ ]+... +[ ]+8:[ ]+R_LARCH_64_PCREL[ ]+.L3 +[ ]+10:[ ]+R_LARCH_ADD64[ ]+.L3 +[ ]+10:[ ]+R_LARCH_SUB64[ ]+.L2 + +Disassembly[ ]+of[ ]+section[ ]+sx: + +0*00000000[ ]+<.L3>: +[ ]+0:[ ]+fffffff4[ ]+.word[ ]+0xfffffff4 +[ ]+4:[ ]+fffffff4[ ]+.word[ ]+0xfffffff4 +[ ]+8:[ ]+ffffffff[ ]+.word[ ]+0xffffffff + +0*0000000c[ ]+<.L4>: +[ ]+... +[ ]+c:[ ]+R_LARCH_ADD32[ ]+.L4 +[ ]+c:[ ]+R_LARCH_SUB32[ ]+.L5 +[ ]+10:[ ]+R_LARCH_ADD64[ ]+.L4 +[ ]+10:[ ]+R_LARCH_SUB64[ ]+.L5 + +Disassembly[ ]+of[ ]+section[ ]+sy: + +0*00000000[ ]+<.L5>: +[ ]+... +[ ]+0:[ ]+R_LARCH_32_PCREL[ ]+.L1 +[ ]+4:[ ]+R_LARCH_32_PCREL[ ]+.L3\+0x4 +[ ]+8:[ ]+R_LARCH_64_PCREL[ ]+.L1\+0x8 +[ ]+10:[ ]+R_LARCH_64_PCREL[ ]+.L3\+0x10 + +Disassembly[ ]+of[ ]+section[ ]+sz: + +0*00000000[ ]+<sz>: +[ ]+0:[ ]+00000000[ ]+.word[ ]+0x00000000 +[ ]+0:[ ]+R_LARCH_ADD32[ ]+.L1 +[ ]+0:[ ]+R_LARCH_SUB32[ ]+.L2 +[ ]+4:[ ]+fffffff4[ ]+.word[ ]+0xfffffff4 +[ ]+... +[ ]+8:[ ]+R_LARCH_ADD32[ ]+.L3 +[ ]+8:[ ]+R_LARCH_SUB32[ ]+.L5 +[ ]+c:[ ]+R_LARCH_ADD64[ ]+.L1 +[ ]+c:[ ]+R_LARCH_SUB64[ ]+.L2 +[ ]+14:[ ]+fffffff4[ ]+.word[ ]+0xfffffff4 +[ ]+18:[ ]+ffffffff[ ]+.word[ ]+0xffffffff +[ ]+... +[ ]+1c:[ ]+R_LARCH_ADD64[ ]+.L3 +[ ]+1c:[ ]+R_LARCH_SUB64[ ]+.L5 diff --git a/gas/testsuite/gas/loongarch/pcrel_relax.s b/gas/testsuite/gas/loongarch/pcrel_relax.s new file mode 100644 index 00000000..ded275fa --- /dev/null +++ b/gas/testsuite/gas/loongarch/pcrel_relax.s @@ -0,0 +1,46 @@ + .section .text +.L1: + # 32_pcrel + .4byte .L3-.L1 + # add32+sub32 + .4byte .L3-.L1 +.L2: + # 64_pcrel + .8byte .L3-.L2 + # add64+sub64 + .8byte .L3-.L2 + + .section sx +.L3: + # no relocation + .4byte .L3-.L4 + .8byte .L3-.L4 +.L4: + # add32+sub32 + .4byte .L4-.L5 + # add64+sub64 + .8byte .L4-.L5 + + .section sy +.L5: + # 32_pcrel + .4byte .L1-.L5 + .4byte .L3-.L5 + # 64_pcrel + .8byte .L1-.L5 + .8byte .L3-.L5 + + .section sz + # add32+sub32 + .4byte .L1-.L2 + # no relocation + .4byte .L3-.L4 + # add32+sub32 + .4byte .L3-.L5 + + #add64+sub64 + .8byte .L1-.L2 + # no relocation + .8byte .L3-.L4 + #add64+sub64 + .8byte .L3-.L5 diff --git a/gas/testsuite/gas/loongarch/privilege_op.d b/gas/testsuite/gas/loongarch/privilege_op.d index 12d4790a..73925f21 100644 --- a/gas/testsuite/gas/loongarch/privilege_op.d +++ b/gas/testsuite/gas/loongarch/privilege_op.d @@ -15,10 +15,10 @@ Disassembly of section .text: [ ]+14:[ ]+04fffca4 [ ]+csrxchg[ ]+[ ]+\$a0, \$a1, 0x3fff [ ]+18:[ ]+060000a0 [ ]+cacop[ ]+[ ]+0x0, \$a1, 0 [ ]+1c:[ ]+060000bf [ ]+cacop[ ]+[ ]+0x1f, \$a1, 0 -[ ]+20:[ ]+061ffca0 [ ]+cacop[ ]+[ ]+0x0, \$a1, 2047\(0x7ff\) -[ ]+24:[ ]+061ffcbf [ ]+cacop[ ]+[ ]+0x1f, \$a1, 2047\(0x7ff\) -[ ]+28:[ ]+062004a0 [ ]+cacop[ ]+[ ]+0x0, \$a1, -2047\(0x801\) -[ ]+2c:[ ]+062004bf [ ]+cacop[ ]+[ ]+0x1f, \$a1, -2047\(0x801\) +[ ]+20:[ ]+061ffca0 [ ]+cacop[ ]+[ ]+0x0, \$a1, 2047 +[ ]+24:[ ]+061ffcbf [ ]+cacop[ ]+[ ]+0x1f, \$a1, 2047 +[ ]+28:[ ]+062004a0 [ ]+cacop[ ]+[ ]+0x0, \$a1, -2047 +[ ]+2c:[ ]+062004bf [ ]+cacop[ ]+[ ]+0x1f, \$a1, -2047 [ ]+30:[ ]+064000a4 [ ]+lddir[ ]+[ ]+\$a0, \$a1, 0x0 [ ]+34:[ ]+0643fca4 [ ]+lddir[ ]+[ ]+\$a0, \$a1, 0xff [ ]+38:[ ]+064400a0 [ ]+ldpte[ ]+[ ]+\$a1, 0x0 diff --git a/gas/testsuite/gas/loongarch/raw-insn.d b/gas/testsuite/gas/loongarch/raw-insn.d new file mode 100644 index 00000000..64980e47 --- /dev/null +++ b/gas/testsuite/gas/loongarch/raw-insn.d @@ -0,0 +1,11 @@ +#as: +#objdump: -dr + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 <target>: +[ ]+0:[ ]+00000000[ ]+.word[ ]+0x00000000 +[ ]+4:[ ]+feedf00d[ ]+.word[ ]+0xfeedf00d diff --git a/gas/testsuite/gas/loongarch/raw-insn.s b/gas/testsuite/gas/loongarch/raw-insn.s new file mode 100644 index 00000000..528b1526 --- /dev/null +++ b/gas/testsuite/gas/loongarch/raw-insn.s @@ -0,0 +1,7 @@ +target: + .word 0 + # Given how the LoongArch encoding space is apparently centrally- + # managed and sequentially allocated in chunks of prefixes, it is + # highly unlikely this would become a valid LoongArch instruction in + # the foreseeable future. + .word 0xfeedf00d diff --git a/gas/testsuite/gas/loongarch/relax_align.d b/gas/testsuite/gas/loongarch/relax_align.d new file mode 100644 index 00000000..1810eb4c --- /dev/null +++ b/gas/testsuite/gas/loongarch/relax_align.d @@ -0,0 +1,26 @@ +#as: +#objdump: -dr +#skip: loongarch32-*-* + +.*:[ ]+file format .* + + +Disassembly of section .text: + +00000000.* <L1>: +[ ]+0:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 +[ ]+0:[ ]+R_LARCH_PCALA_HI20[ ]+L1 +[ ]+0:[ ]+R_LARCH_RELAX[ ]+\*ABS\* +[ ]+4:[ ]+02c00084[ ]+addi\.d[ ]+\$a0,[ ]+\$a0,[ ]+0 +[ ]+4:[ ]+R_LARCH_PCALA_LO12[ ]+L1 +[ ]+4:[ ]+R_LARCH_RELAX[ ]+\*ABS\* +[ ]+8:[ ]+03400000[ ]+nop[ ]+ +[ ]+8:[ ]+R_LARCH_ALIGN[ ]+\*ABS\*\+0xc +[ ]+c:[ ]+03400000[ ]+nop[ ]+ +[ ]+10:[ ]+03400000[ ]+nop[ ]+ +[ ]+14:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 +[ ]+14:[ ]+R_LARCH_PCALA_HI20[ ]+L1 +[ ]+14:[ ]+R_LARCH_RELAX[ ]+\*ABS\* +[ ]+18:[ ]+02c00084[ ]+addi\.d[ ]+\$a0,[ ]+\$a0,[ ]+0 +[ ]+18:[ ]+R_LARCH_PCALA_LO12[ ]+L1 +[ ]+18:[ ]+R_LARCH_RELAX[ ]+\*ABS\* diff --git a/gas/testsuite/gas/loongarch/relax_align.s b/gas/testsuite/gas/loongarch/relax_align.s new file mode 100644 index 00000000..3880d783 --- /dev/null +++ b/gas/testsuite/gas/loongarch/relax_align.s @@ -0,0 +1,5 @@ + .text +L1: + la.local $a0, L1 + .align 4 + la.local $a0, L1 diff --git a/gas/testsuite/gas/loongarch/reloc.d b/gas/testsuite/gas/loongarch/reloc.d index 6f5f110b..c3820c55 100644 --- a/gas/testsuite/gas/loongarch/reloc.d +++ b/gas/testsuite/gas/loongarch/reloc.d @@ -8,7 +8,7 @@ Disassembly of section .text: 00000000.* <.text>: -[ ]+0:[ ]+03400000[ ]+andi[ ]+\$zero,[ ]+\$zero,[ ]+0x0 +[ ]+0:[ ]+03400000[ ]+nop[ ]+ [ ]+4:[ ]+58000085[ ]+beq[ ]+\$a0,[ ]+\$a1,[ ]+0[ ]+#[ ]+0x4 [ ]+4:[ ]+R_LARCH_B16[ ]+.L1 [ ]+8:[ ]+5c000085[ ]+bne[ ]+\$a0,[ ]+\$a1,[ ]+0[ ]+#[ ]+0x8 diff --git a/gas/testsuite/gas/loongarch/uleb128.d b/gas/testsuite/gas/loongarch/uleb128.d new file mode 100644 index 00000000..1a6730f3 --- /dev/null +++ b/gas/testsuite/gas/loongarch/uleb128.d @@ -0,0 +1,36 @@ +#as: +#objdump: -Dr +#skip: loongarch32-*-* + +.*:[ ]+file format .* + + +Disassembly of section .data: + +00000000.* <L1-0x5>: +[ ]*0:[ ]*80030201[ ]*\.word[ ]*0x80030201 +[ ]*3:[ ]*R_LARCH_ADD_ULEB128[ ]*L2 +[ ]*3:[ ]*R_LARCH_SUB_ULEB128[ ]*L1 +[ ]*\.\.\. + +[ ]*0000000000000005[ ]*<L1>: +[ ]*\.\.\. +[ ]*81:[ ]*ff040000[ ]*\.word[ ]*0xff040000 +[ ]*85:[ ]*cacop[ ]*0x1f,[ ]*\$t3,[ ]*1 + +[ ]*0000000000000086[ ]*<L2>: +[ ]*86:[ ]*07060005[ ]*\.word[ ]*0x07060005 +[ ]*8a:[ ]*x86inc\.b[ ]*\$a0 +[ ]*8a:[ ]*R_LARCH_ADD_ULEB128[ ]*L4 +[ ]*8a:[ ]*R_LARCH_SUB_ULEB128[ ]*L3 + +[ ]*000000000000008d[ ]*<L3>: +[ ]*\.\.\. +[ ]*4089:[ ]*ff080000[ ]*\.word[ ]*0xff080000 +[ ]*408d:[ ]*\.word[ ]*0x09ffffff + +[ ]*0000000000004090[ ]*<L4>: +[ ]*4090:[ ]*09090909[ ]*\.word[ ]*0x09090909 +[ ]*4094:[ ]*09090909[ ]*\.word[ ]*0x09090909 +[ ]*4098:[ ]*09090909[ ]*\.word[ ]*0x09090909 +[ ]*409c:[ ]*09090909[ ]*\.word[ ]*0x09090909 diff --git a/gas/testsuite/gas/loongarch/uleb128.s b/gas/testsuite/gas/loongarch/uleb128.s new file mode 100644 index 00000000..104a8956 --- /dev/null +++ b/gas/testsuite/gas/loongarch/uleb128.s @@ -0,0 +1,20 @@ + .data + .byte 1, 2, 3 + .uleb128 L2 - L1 +L1: + .space 128 - 2 + .byte 4 + .p2align 1, 0xff +L2: + .byte 5 + + .p2align 2 + .byte 6, 7 + .uleb128 L4 - L3 +L3: + .space 128*128 - 2 + .byte 8 + .p2align 2, 0xff +L4: + .byte 9 + .p2align 4, 9 diff --git a/gas/testsuite/gas/loongarch/vector.d b/gas/testsuite/gas/loongarch/vector.d new file mode 100644 index 00000000..1a092bca --- /dev/null +++ b/gas/testsuite/gas/loongarch/vector.d @@ -0,0 +1,1461 @@ +#as: +#objdump: -dr +#skip: loongarch32-*-* + +.*:[ ]+file format .* + + +Disassembly of section .text: + +00000000.* <.text>: +[ ]+0:[ ]+09118820[ ]+vfmadd.s[ ]+\$vr0,[ ]+\$vr1,[ ]+\$vr2,[ ]+\$vr3 +[ ]+4:[ ]+09518820[ ]+vfmsub.s[ ]+\$vr0,[ ]+\$vr1,[ ]+\$vr2,[ ]+\$vr3 +[ ]+8:[ ]+09918820[ ]+vfnmadd.s[ ]+\$vr0,[ ]+\$vr1,[ ]+\$vr2,[ ]+\$vr3 +[ ]+c:[ ]+09d18820[ ]+vfnmsub.s[ ]+\$vr0,[ ]+\$vr1,[ ]+\$vr2,[ ]+\$vr3 +[ ]+10:[ ]+0a118820[ ]+xvfmadd.s[ ]+\$xr0,[ ]+\$xr1,[ ]+\$xr2,[ ]+\$xr3 +[ ]+14:[ ]+0a518820[ ]+xvfmsub.s[ ]+\$xr0,[ ]+\$xr1,[ ]+\$xr2,[ ]+\$xr3 +[ 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]+1650:[ ]+776d0420[ ]+xvssrarni.wu.d[ ]+\$xr0,[ ]+\$xr1,[ ]+0x1 +[ ]+1654:[ ]+776e0420[ ]+xvssrarni.du.q[ ]+\$xr0,[ ]+\$xr1,[ ]+0x1 +[ ]+1658:[ ]+77800420[ ]+xvextrins.d[ ]+\$xr0,[ ]+\$xr1,[ ]+0x1 +[ ]+165c:[ ]+77840420[ ]+xvextrins.w[ ]+\$xr0,[ ]+\$xr1,[ ]+0x1 +[ ]+1660:[ ]+77880420[ ]+xvextrins.h[ ]+\$xr0,[ ]+\$xr1,[ ]+0x1 +[ ]+1664:[ ]+778c0420[ ]+xvextrins.b[ ]+\$xr0,[ ]+\$xr1,[ ]+0x1 +[ ]+1668:[ ]+77900420[ ]+xvshuf4i.b[ ]+\$xr0,[ ]+\$xr1,[ ]+0x1 +[ ]+166c:[ ]+77940420[ ]+xvshuf4i.h[ ]+\$xr0,[ ]+\$xr1,[ ]+0x1 +[ ]+1670:[ ]+77980420[ ]+xvshuf4i.w[ ]+\$xr0,[ ]+\$xr1,[ ]+0x1 +[ ]+1674:[ ]+779c0420[ ]+xvshuf4i.d[ ]+\$xr0,[ ]+\$xr1,[ ]+0x1 +[ ]+1678:[ ]+77c40420[ ]+xvbitseli.b[ ]+\$xr0,[ ]+\$xr1,[ ]+0x1 +[ ]+167c:[ ]+77d00420[ ]+xvandi.b[ ]+\$xr0,[ ]+\$xr1,[ ]+0x1 +[ ]+1680:[ ]+77d40420[ ]+xvori.b[ ]+\$xr0,[ ]+\$xr1,[ ]+0x1 +[ ]+1684:[ ]+77d80420[ ]+xvxori.b[ ]+\$xr0,[ ]+\$xr1,[ ]+0x1 +[ ]+1688:[ ]+77dc0420[ ]+xvnori.b[ ]+\$xr0,[ ]+\$xr1,[ ]+0x1 +[ ]+168c:[ ]+77e00020[ ]+xvldi[ ]+\$xr0,[ ]+1 +[ ]+1690:[ ]+77e18020[ ]+xvldi[ ]+\$xr0,[ ]+3073 +[ ]+1694:[ ]+77e08020[ ]+xvldi[ ]+\$xr0,[ ]+1025 +[ ]+1698:[ ]+77e10020[ ]+xvldi[ ]+\$xr0,[ ]+2049 +[ ]+169c:[ ]+77e00020[ ]+xvldi[ ]+\$xr0,[ ]+1 +[ ]+16a0:[ ]+77e40420[ ]+xvpermi.w[ ]+\$xr0,[ ]+\$xr1,[ ]+0x1 +[ ]+16a4:[ ]+77e80420[ ]+xvpermi.d[ ]+\$xr0,[ ]+\$xr1,[ ]+0x1 +[ ]+16a8:[ ]+77ec0420[ ]+xvpermi.q[ ]+\$xr0,[ ]+\$xr1,[ ]+0x1 diff --git a/gas/testsuite/gas/loongarch/vector.s b/gas/testsuite/gas/loongarch/vector.s new file mode 100644 index 00000000..fe0369e7 --- /dev/null +++ b/gas/testsuite/gas/loongarch/vector.s @@ -0,0 +1,1451 @@ +vfmadd.s $vr0, $vr1, $vr2, $vr3 +vfmsub.s $vr0, $vr1, $vr2, $vr3 +vfnmadd.s $vr0, $vr1, $vr2, $vr3 +vfnmsub.s $vr0, $vr1, $vr2, $vr3 +xvfmadd.s $xr0, $xr1, $xr2, $xr3 +xvfmsub.s $xr0, $xr1, $xr2, $xr3 +xvfnmadd.s $xr0, $xr1, $xr2, $xr3 +xvfnmsub.s $xr0, $xr1, $xr2, $xr3 +vfcmp.caf.s $vr0, $vr1, $vr2 +vfcmp.saf.s $vr0, $vr1, $vr2 +vfcmp.clt.s $vr0, $vr1, $vr2 +vfcmp.slt.s $vr0, $vr1, $vr2 +vfcmp.ceq.s $vr0, $vr1, $vr2 +vfcmp.seq.s $vr0, $vr1, $vr2 +vfcmp.cle.s $vr0, $vr1, $vr2 +vfcmp.sle.s $vr0, $vr1, $vr2 +vfcmp.cun.s $vr0, $vr1, $vr2 +vfcmp.sun.s $vr0, $vr1, $vr2 +vfcmp.cult.s $vr0, $vr1, $vr2 +vfcmp.sult.s $vr0, $vr1, $vr2 +vfcmp.cueq.s $vr0, $vr1, $vr2 +vfcmp.sueq.s $vr0, $vr1, $vr2 +vfcmp.cule.s $vr0, $vr1, $vr2 +vfcmp.sule.s $vr0, $vr1, $vr2 +vfcmp.cne.s $vr0, $vr1, $vr2 +vfcmp.sne.s $vr0, $vr1, $vr2 +vfcmp.cor.s $vr0, $vr1, $vr2 +vfcmp.sor.s $vr0, $vr1, $vr2 +vfcmp.cune.s $vr0, $vr1, $vr2 +vfcmp.sune.s $vr0, $vr1, $vr2 +xvfcmp.caf.s $xr0, $xr1, $xr2 +xvfcmp.saf.s $xr0, $xr1, $xr2 +xvfcmp.clt.s $xr0, $xr1, $xr2 +xvfcmp.slt.s $xr0, $xr1, $xr2 +xvfcmp.ceq.s $xr0, $xr1, $xr2 +xvfcmp.seq.s $xr0, $xr1, $xr2 +xvfcmp.cle.s $xr0, $xr1, $xr2 +xvfcmp.sle.s $xr0, $xr1, $xr2 +xvfcmp.cun.s $xr0, $xr1, $xr2 +xvfcmp.sun.s $xr0, $xr1, $xr2 +xvfcmp.cult.s $xr0, $xr1, $xr2 +xvfcmp.sult.s $xr0, $xr1, $xr2 +xvfcmp.cueq.s $xr0, $xr1, $xr2 +xvfcmp.sueq.s $xr0, $xr1, $xr2 +xvfcmp.cule.s $xr0, $xr1, $xr2 +xvfcmp.sule.s $xr0, $xr1, $xr2 +xvfcmp.cne.s $xr0, $xr1, $xr2 +xvfcmp.sne.s $xr0, $xr1, $xr2 +xvfcmp.cor.s $xr0, $xr1, $xr2 +xvfcmp.sor.s $xr0, $xr1, $xr2 +xvfcmp.cune.s $xr0, $xr1, $xr2 +xvfcmp.sune.s $xr0, $xr1, $xr2 +vbitsel.v $vr0, $vr1, $vr2, $vr3 +xvbitsel.v $xr0, $xr1, $xr2, $xr3 +vshuf.b $vr0, $vr1, $vr2, $vr3 +xvshuf.b $xr0, $xr1, $xr2, $xr3 +vfmadd.d $vr0, $vr1, $vr2, $vr3 +vfmsub.d $vr0, $vr1, $vr2, $vr3 +vfnmadd.d $vr0, $vr1, $vr2, $vr3 +vfnmsub.d $vr0, $vr1, $vr2, $vr3 +xvfmadd.d $xr0, $xr1, $xr2, $xr3 +xvfmsub.d $xr0, $xr1, $xr2, $xr3 +xvfnmadd.d $xr0, $xr1, $xr2, $xr3 +xvfnmsub.d $xr0, $xr1, $xr2, $xr3 +vfcmp.caf.d $vr0, $vr1, $vr2 +vfcmp.saf.d $vr0, $vr1, $vr2 +vfcmp.clt.d $vr0, $vr1, $vr2 +vfcmp.slt.d $vr0, $vr1, $vr2 +vfcmp.ceq.d $vr0, $vr1, $vr2 +vfcmp.seq.d $vr0, $vr1, $vr2 +vfcmp.cle.d $vr0, $vr1, $vr2 +vfcmp.sle.d $vr0, $vr1, $vr2 +vfcmp.cun.d $vr0, $vr1, $vr2 +vfcmp.sun.d $vr0, $vr1, $vr2 +vfcmp.cult.d $vr0, $vr1, $vr2 +vfcmp.sult.d $vr0, $vr1, $vr2 +vfcmp.cueq.d $vr0, $vr1, $vr2 +vfcmp.sueq.d $vr0, $vr1, $vr2 +vfcmp.cule.d $vr0, $vr1, $vr2 +vfcmp.sule.d $vr0, $vr1, $vr2 +vfcmp.cne.d $vr0, $vr1, $vr2 +vfcmp.sne.d $vr0, $vr1, $vr2 +vfcmp.cor.d $vr0, $vr1, $vr2 +vfcmp.sor.d $vr0, $vr1, $vr2 +vfcmp.cune.d $vr0, $vr1, $vr2 +vfcmp.sune.d $vr0, $vr1, $vr2 +xvfcmp.caf.d $xr0, $xr1, $xr2 +xvfcmp.saf.d $xr0, $xr1, $xr2 +xvfcmp.clt.d $xr0, $xr1, $xr2 +xvfcmp.slt.d $xr0, $xr1, $xr2 +xvfcmp.ceq.d $xr0, $xr1, $xr2 +xvfcmp.seq.d $xr0, $xr1, $xr2 +xvfcmp.cle.d $xr0, $xr1, $xr2 +xvfcmp.sle.d $xr0, $xr1, $xr2 +xvfcmp.cun.d $xr0, $xr1, $xr2 +xvfcmp.sun.d $xr0, $xr1, $xr2 +xvfcmp.cult.d $xr0, $xr1, $xr2 +xvfcmp.sult.d $xr0, $xr1, $xr2 +xvfcmp.cueq.d $xr0, $xr1, $xr2 +xvfcmp.sueq.d $xr0, $xr1, $xr2 +xvfcmp.cule.d $xr0, $xr1, $xr2 +xvfcmp.sule.d $xr0, $xr1, $xr2 +xvfcmp.cne.d $xr0, $xr1, $xr2 +xvfcmp.sne.d $xr0, $xr1, $xr2 +xvfcmp.cor.d $xr0, $xr1, $xr2 +xvfcmp.sor.d $xr0, $xr1, $xr2 +xvfcmp.cune.d $xr0, $xr1, $xr2 +xvfcmp.sune.d $xr0, $xr1, $xr2 +vld $vr0, $r1, 1 +vst $vr0, $r1, 1 +xvld $xr0, $r1, 1 +xvst $xr0, $r1, 1 +vldx $vr0, $r1, $r2 +vstx $vr0, $r1, $r2 +xvldx $xr0, $r1, $r2 +xvstx $xr0, $r1, $r2 +vldrepl.d $vr0, $r1, 1000 +vldrepl.w $vr0, $r1, 100 +vldrepl.h $vr0, $r1, 10 +vldrepl.b $vr0, $r1, 1 +vstelm.d $vr0, $r1, 1000, 1 +vstelm.w $vr0, $r1, 100, 1 +vstelm.h $vr0, $r1, 10, 1 +vstelm.b $vr0, $r1, 1, 1 +xvldrepl.d $xr0, $r1, 1000 +xvldrepl.w $xr0, $r1, 100 +xvldrepl.h $xr0, $r1, 10 +xvldrepl.b $xr0, $r1, 1 +xvstelm.d $xr0, $r1, 1000, 1 +xvstelm.w $xr0, $r1, 100, 1 +xvstelm.h $xr0, $r1, 10, 1 +xvstelm.b $xr0, $r1, 1, 1 +vseq.b $vr0, $vr1, $vr2 +vseq.h $vr0, $vr1, $vr2 +vseq.w $vr0, $vr1, $vr2 +vseq.d $vr0, $vr1, $vr2 +vsle.b $vr0, $vr1, $vr2 +vsle.h $vr0, $vr1, $vr2 +vsle.w $vr0, $vr1, $vr2 +vsle.d $vr0, $vr1, $vr2 +vsle.bu $vr0, $vr1, $vr2 +vsle.hu $vr0, $vr1, $vr2 +vsle.wu $vr0, $vr1, $vr2 +vsle.du $vr0, $vr1, $vr2 +vslt.b $vr0, $vr1, $vr2 +vslt.h $vr0, $vr1, $vr2 +vslt.w $vr0, $vr1, $vr2 +vslt.d $vr0, $vr1, $vr2 +vslt.bu $vr0, $vr1, $vr2 +vslt.hu $vr0, $vr1, $vr2 +vslt.wu $vr0, $vr1, $vr2 +vslt.du $vr0, $vr1, $vr2 +vadd.b $vr0, $vr1, $vr2 +vadd.h $vr0, $vr1, $vr2 +vadd.w $vr0, $vr1, $vr2 +vadd.d $vr0, $vr1, $vr2 +vsub.b $vr0, $vr1, $vr2 +vsub.h $vr0, $vr1, $vr2 +vsub.w $vr0, $vr1, $vr2 +vsub.d $vr0, $vr1, $vr2 +vsadd.b $vr0, $vr1, $vr2 +vsadd.h $vr0, $vr1, $vr2 +vsadd.w $vr0, $vr1, $vr2 +vsadd.d $vr0, $vr1, $vr2 +vssub.b $vr0, $vr1, $vr2 +vssub.h $vr0, $vr1, $vr2 +vssub.w $vr0, $vr1, $vr2 +vssub.d $vr0, $vr1, $vr2 +vsadd.bu $vr0, $vr1, $vr2 +vsadd.hu $vr0, $vr1, $vr2 +vsadd.wu $vr0, $vr1, $vr2 +vsadd.du $vr0, $vr1, $vr2 +vssub.bu $vr0, $vr1, $vr2 +vssub.hu $vr0, $vr1, $vr2 +vssub.wu $vr0, $vr1, $vr2 +vssub.du $vr0, $vr1, $vr2 +vhaddw.h.b $vr0, $vr1, $vr2 +vhaddw.w.h $vr0, $vr1, $vr2 +vhaddw.d.w $vr0, $vr1, $vr2 +vhaddw.q.d $vr0, $vr1, $vr2 +vhsubw.h.b $vr0, $vr1, $vr2 +vhsubw.w.h $vr0, $vr1, $vr2 +vhsubw.d.w $vr0, $vr1, $vr2 +vhsubw.q.d $vr0, $vr1, $vr2 +vhaddw.hu.bu $vr0, $vr1, $vr2 +vhaddw.wu.hu $vr0, $vr1, $vr2 +vhaddw.du.wu $vr0, $vr1, $vr2 +vhaddw.qu.du $vr0, $vr1, $vr2 +vhsubw.hu.bu $vr0, $vr1, $vr2 +vhsubw.wu.hu $vr0, $vr1, $vr2 +vhsubw.du.wu $vr0, $vr1, $vr2 +vhsubw.qu.du $vr0, $vr1, $vr2 +vadda.b $vr0, $vr1, $vr2 +vadda.h $vr0, $vr1, $vr2 +vadda.w $vr0, $vr1, $vr2 +vadda.d $vr0, $vr1, $vr2 +vabsd.b $vr0, $vr1, $vr2 +vabsd.h $vr0, $vr1, $vr2 +vabsd.w $vr0, $vr1, $vr2 +vabsd.d $vr0, $vr1, $vr2 +vabsd.bu $vr0, $vr1, $vr2 +vabsd.hu $vr0, $vr1, $vr2 +vabsd.wu $vr0, $vr1, $vr2 +vabsd.du $vr0, $vr1, $vr2 +vavg.b $vr0, $vr1, $vr2 +vavg.h $vr0, $vr1, $vr2 +vavg.w $vr0, $vr1, $vr2 +vavg.d $vr0, $vr1, $vr2 +vavg.bu $vr0, $vr1, $vr2 +vavg.hu $vr0, $vr1, $vr2 +vavg.wu $vr0, $vr1, $vr2 +vavg.du $vr0, $vr1, $vr2 +vavgr.b $vr0, $vr1, $vr2 +vavgr.h $vr0, $vr1, $vr2 +vavgr.w $vr0, $vr1, $vr2 +vavgr.d $vr0, $vr1, $vr2 +vavgr.bu $vr0, $vr1, $vr2 +vavgr.hu $vr0, $vr1, $vr2 +vavgr.wu $vr0, $vr1, $vr2 +vavgr.du $vr0, $vr1, $vr2 +vmax.b $vr0, $vr1, $vr2 +vmax.h $vr0, $vr1, $vr2 +vmax.w $vr0, $vr1, $vr2 +vmax.d $vr0, $vr1, $vr2 +vmin.b $vr0, $vr1, $vr2 +vmin.h $vr0, $vr1, $vr2 +vmin.w $vr0, $vr1, $vr2 +vmin.d $vr0, $vr1, $vr2 +vmax.bu $vr0, $vr1, $vr2 +vmax.hu $vr0, $vr1, $vr2 +vmax.wu $vr0, $vr1, $vr2 +vmax.du $vr0, $vr1, $vr2 +vmin.bu $vr0, $vr1, $vr2 +vmin.hu $vr0, $vr1, $vr2 +vmin.wu $vr0, $vr1, $vr2 +vmin.du $vr0, $vr1, $vr2 +vmul.b $vr0, $vr1, $vr2 +vmul.h $vr0, $vr1, $vr2 +vmul.w $vr0, $vr1, $vr2 +vmul.d $vr0, $vr1, $vr2 +vmuh.b $vr0, $vr1, $vr2 +vmuh.h $vr0, $vr1, $vr2 +vmuh.w $vr0, $vr1, $vr2 +vmuh.d $vr0, $vr1, $vr2 +vmuh.bu $vr0, $vr1, $vr2 +vmuh.hu $vr0, $vr1, $vr2 +vmuh.wu $vr0, $vr1, $vr2 +vmuh.du $vr0, $vr1, $vr2 +vmadd.b $vr0, $vr1, $vr2 +vmadd.h $vr0, $vr1, $vr2 +vmadd.w $vr0, $vr1, $vr2 +vmadd.d $vr0, $vr1, $vr2 +vmsub.b $vr0, $vr1, $vr2 +vmsub.h $vr0, $vr1, $vr2 +vmsub.w $vr0, $vr1, $vr2 +vmsub.d $vr0, $vr1, $vr2 +vdiv.b $vr0, $vr1, $vr2 +vdiv.h $vr0, $vr1, $vr2 +vdiv.w $vr0, $vr1, $vr2 +vdiv.d $vr0, $vr1, $vr2 +vmod.b $vr0, $vr1, $vr2 +vmod.h $vr0, $vr1, $vr2 +vmod.w $vr0, $vr1, $vr2 +vmod.d $vr0, $vr1, $vr2 +vdiv.bu $vr0, $vr1, $vr2 +vdiv.hu $vr0, $vr1, $vr2 +vdiv.wu $vr0, $vr1, $vr2 +vdiv.du $vr0, $vr1, $vr2 +vmod.bu $vr0, $vr1, $vr2 +vmod.hu $vr0, $vr1, $vr2 +vmod.wu $vr0, $vr1, $vr2 +vmod.du $vr0, $vr1, $vr2 +vsll.b $vr0, $vr1, $vr2 +vsll.h $vr0, $vr1, $vr2 +vsll.w $vr0, $vr1, $vr2 +vsll.d $vr0, $vr1, $vr2 +vsrl.b $vr0, $vr1, $vr2 +vsrl.h $vr0, $vr1, $vr2 +vsrl.w $vr0, $vr1, $vr2 +vsrl.d $vr0, $vr1, $vr2 +vsra.b $vr0, $vr1, $vr2 +vsra.h $vr0, $vr1, $vr2 +vsra.w $vr0, $vr1, $vr2 +vsra.d $vr0, $vr1, $vr2 +vrotr.b $vr0, $vr1, $vr2 +vrotr.h $vr0, $vr1, $vr2 +vrotr.w $vr0, $vr1, $vr2 +vrotr.d $vr0, $vr1, $vr2 +vsrlr.b $vr0, $vr1, $vr2 +vsrlr.h $vr0, $vr1, $vr2 +vsrlr.w $vr0, $vr1, $vr2 +vsrlr.d $vr0, $vr1, $vr2 +vsrar.b $vr0, $vr1, $vr2 +vsrar.h $vr0, $vr1, $vr2 +vsrar.w $vr0, $vr1, $vr2 +vsrar.d $vr0, $vr1, $vr2 +vsrln.b.h $vr0, $vr1, $vr2 +vsrln.h.w $vr0, $vr1, $vr2 +vsrln.w.d $vr0, $vr1, $vr2 +vsran.b.h $vr0, $vr1, $vr2 +vsran.h.w $vr0, $vr1, $vr2 +vsran.w.d $vr0, $vr1, $vr2 +vsrlrn.b.h $vr0, $vr1, $vr2 +vsrlrn.h.w $vr0, $vr1, $vr2 +vsrlrn.w.d $vr0, $vr1, $vr2 +vsrarn.b.h $vr0, $vr1, $vr2 +vsrarn.h.w $vr0, $vr1, $vr2 +vsrarn.w.d $vr0, $vr1, $vr2 +vssrln.b.h $vr0, $vr1, $vr2 +vssrln.h.w $vr0, $vr1, $vr2 +vssrln.w.d $vr0, $vr1, $vr2 +vssran.b.h $vr0, $vr1, $vr2 +vssran.h.w $vr0, $vr1, $vr2 +vssran.w.d $vr0, $vr1, $vr2 +vssrlrn.b.h $vr0, $vr1, $vr2 +vssrlrn.h.w $vr0, $vr1, $vr2 +vssrlrn.w.d $vr0, $vr1, $vr2 +vssrarn.b.h $vr0, $vr1, $vr2 +vssrarn.h.w $vr0, $vr1, $vr2 +vssrarn.w.d $vr0, $vr1, $vr2 +vssrln.bu.h $vr0, $vr1, $vr2 +vssrln.hu.w $vr0, $vr1, $vr2 +vssrln.wu.d $vr0, $vr1, $vr2 +vssran.bu.h $vr0, $vr1, $vr2 +vssran.hu.w $vr0, $vr1, $vr2 +vssran.wu.d $vr0, $vr1, $vr2 +vssrlrn.bu.h $vr0, $vr1, $vr2 +vssrlrn.hu.w $vr0, $vr1, $vr2 +vssrlrn.wu.d $vr0, $vr1, $vr2 +vssrarn.bu.h $vr0, $vr1, $vr2 +vssrarn.hu.w $vr0, $vr1, $vr2 +vssrarn.wu.d $vr0, $vr1, $vr2 +vbitclr.b $vr0, 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$xr0, 1 +xvrepli.h $xr0, 1 +xvrepli.w $xr0, 1 +xvldi $xr0, 1 +xvpermi.w $xr0, $xr1, 1 +xvpermi.d $xr0, $xr1, 1 +xvpermi.q $xr0, $xr1, 1 diff --git a/gas/testsuite/lib/gas-defs.exp b/gas/testsuite/lib/gas-defs.exp index 6074c2ee..e64e45da 100644 --- a/gas/testsuite/lib/gas-defs.exp +++ b/gas/testsuite/lib/gas-defs.exp @@ -361,9 +361,6 @@ proc verbose_eval { expr { level 1 } } { # that version gets released, and has been out in the world for a few # months at least, it may be safe to delete this copy. -if { [istarget loongarch*-*-*] } { - rename prune_warnings prune_warnings_other -} if ![string length [info proc prune_warnings]] { # # prune_warnings -- delete various system verbosities from TEXT. diff --git a/include/coff/loongarch64.h b/include/coff/loongarch64.h new file mode 100644 index 00000000..b80ca42a --- /dev/null +++ b/include/coff/loongarch64.h @@ -0,0 +1,61 @@ +/* LoongArch64 COFF support for BFD. + Copyright (C) 2022 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#define COFFLOONGARCH64 1 + +#define L_LNNO_SIZE 2 +#define INCLUDE_COMDAT_FIELDS_IN_AUXENT +#include "coff/external.h" + +#define F_LOONGARCH64_ARCHITECTURE_MASK (0x4000) + +#define LOONGARCH64MAGIC 0x6264 /* From Microsoft specification. */ + +#undef BADMAG +#define BADMAG(x) ((x).f_magic != LOONGARCH64MAGIC) +#define LOONGARCH64 1 /* Customize coffcode.h. */ + +#define IMAGE_NT_OPTIONAL_HDR64_MAGIC 0x20b + +#define OMAGIC 0404 /* Object files, eg as output. */ +#define ZMAGIC IMAGE_NT_OPTIONAL_HDR64_MAGIC /* Demand load format, eg normal ld output 0x10b. */ +#define STMAGIC 0401 /* Target shlib. */ +#define SHMAGIC 0443 /* Host shlib. */ + +/* define some NT default values */ +/* #define NT_IMAGE_BASE 0x400000 moved to internal.h */ +#define NT_SECTION_ALIGNMENT 0x1000 +#define NT_FILE_ALIGNMENT 0x200 +#define NT_DEF_RESERVE 0x100000 +#define NT_DEF_COMMIT 0x1000 + +/* We use the .rdata section to hold read only data. */ +#define _LIT ".rdata" + +/********************** RELOCATION DIRECTIVES **********************/ +struct external_reloc +{ + char r_vaddr[4]; + char r_symndx[4]; + char r_type[2]; + char r_offset[4]; +}; + +#define RELOC struct external_reloc +#define RELSZ 14 diff --git a/include/coff/pe.h b/include/coff/pe.h index 558cf0e1..2423565c 100644 --- a/include/coff/pe.h +++ b/include/coff/pe.h @@ -163,6 +163,7 @@ #define IMAGE_FILE_MACHINE_TRICORE 0x0520 #define IMAGE_FILE_MACHINE_WCEMIPSV2 0x0169 #define IMAGE_FILE_MACHINE_AMD64 0x8664 +#define IMAGE_FILE_MACHINE_LOONGARCH64 0x6264 #define IMAGE_SUBSYSTEM_UNKNOWN 0 #define IMAGE_SUBSYSTEM_NATIVE 1 diff --git a/include/elf/loongarch.h b/include/elf/loongarch.h index a6341b46..a35718d7 100644 --- a/include/elf/loongarch.h +++ b/include/elf/loongarch.h @@ -229,6 +229,28 @@ RELOC_NUMBER (R_LARCH_32_PCREL, 99) /* RELAX. */ RELOC_NUMBER (R_LARCH_RELAX, 100) +/* relax delete. */ +RELOC_NUMBER (R_LARCH_DELETE, 101) + +/* relax align. */ +RELOC_NUMBER (R_LARCH_ALIGN, 102) + +/* pcaddi. */ +RELOC_NUMBER (R_LARCH_PCREL20_S2, 103) + +/* cfa. */ +RELOC_NUMBER (R_LARCH_CFA, 104) + +/* DW_CFA_advance_loc. */ +RELOC_NUMBER (R_LARCH_ADD6, 105) +RELOC_NUMBER (R_LARCH_SUB6, 106) + +/* unsigned leb128. */ +RELOC_NUMBER (R_LARCH_ADD_ULEB128, 107) +RELOC_NUMBER (R_LARCH_SUB_ULEB128, 108) + +RELOC_NUMBER (R_LARCH_64_PCREL, 109) + END_RELOC_NUMBERS (R_LARCH_count) /* Processor specific flags for the ELF header e_flags field. */ diff --git a/include/opcode/loongarch.h b/include/opcode/loongarch.h index c3922348..54005d9a 100644 --- a/include/opcode/loongarch.h +++ b/include/opcode/loongarch.h @@ -28,6 +28,8 @@ extern "C" { #endif + #define LARCH_NOP 0x03400000 + typedef uint32_t insn_t; struct loongarch_opcode @@ -118,6 +120,8 @@ dec2 : [1-9][0-9]? const unsigned long pinfo; #define USELESS 0x0l +/* Instruction is a simple alias only for disassembler use. */ +#define INSN_DIS_ALIAS 0x00000001l }; struct hash_control; @@ -172,17 +176,14 @@ dec2 : [1-9][0-9]? extern void loongarch_eliminate_adjacent_repeat_char (char *dest, char c); - extern int loongarch_parse_dis_options (const char *opts_in); - extern void loongarch_disassemble_one ( - int64_t pc, insn_t insn, - int (*fprintf_func) (void *stream, const char *format, ...), void *stream); - extern const char *const loongarch_r_normal_name[32]; extern const char *const loongarch_r_lp64_name[32]; - extern const char *const loongarch_r_lp64_name1[32]; + extern const char *const loongarch_r_lp64_name_deprecated[32]; extern const char *const loongarch_f_normal_name[32]; extern const char *const loongarch_f_lp64_name[32]; - extern const char *const loongarch_f_lp64_name1[32]; + extern const char *const loongarch_f_lp64_name_deprecated[32]; + extern const char *const loongarch_fc_normal_name[4]; + extern const char *const loongarch_fc_numeric_name[4]; extern const char *const loongarch_c_normal_name[8]; extern const char *const loongarch_cr_normal_name[4]; extern const char *const loongarch_v_normal_name[32]; @@ -210,6 +211,9 @@ dec2 : [1-9][0-9]? int use_lsx; int use_lasx; + int use_lvz; + int use_lbt; + int use_la_local_with_abs; int use_la_global_with_pcrel; int use_la_global_with_abs; @@ -224,10 +228,14 @@ dec2 : [1-9][0-9]? #define ase_lsx isa.use_lsx #define ase_lasx isa.use_lasx +#define ase_lvz isa.use_lvz +#define ase_lbt isa.use_lbt + #define ase_labs isa.use_la_local_with_abs #define ase_gpcr isa.use_la_global_with_pcrel #define ase_gabs isa.use_la_global_with_abs + int relax; } LARCH_opts; extern size_t loongarch_insn_length (insn_t insn); diff --git a/ld/emultempl/loongarchelf.em b/ld/emultempl/loongarchelf.em index b688ef7b..53560a69 100644 --- a/ld/emultempl/loongarchelf.em +++ b/ld/emultempl/loongarchelf.em @@ -23,6 +23,7 @@ fragment <<EOF #include "ldmain.h" #include "ldctor.h" #include "elf/loongarch.h" +#include "elfxx-loongarch.h" static void larch_elf_before_allocation (void) @@ -61,6 +62,8 @@ gld${EMULATION_NAME}_after_allocation (void) } } + enum phase_enum *phase = &(expld.dataseg.phase); + bfd_elf${ELFSIZE}_loongarch_set_data_segment_info (&link_info, (int *) phase); /* gld${EMULATION_NAME}_map_segments (need_layout); */ ldelf_map_segments (need_layout); } diff --git a/ld/testsuite/ld-elf/compressed1d.d b/ld/testsuite/ld-elf/compressed1d.d index 9d891c19..b178695e 100644 --- a/ld/testsuite/ld-elf/compressed1d.d +++ b/ld/testsuite/ld-elf/compressed1d.d @@ -4,10 +4,13 @@ #readelf: -SW #xfail: [uses_genelf] #xfail: [riscv_little_endian] +#xfail: loongarch*-*-* # Not all ELF targets use the elf.em emulation... # RISC-V has linker relaxations that delete code, so text label subtractions # do not get resolved at assembly time, which results in a compressed section # for little endian targets; but it is uncompressed for big endian targets. +# LoongArch has linker relaxations that delete code, so text label subtractions +# do not get resolved at assembly time, which results in a compressed section. #failif #... diff --git a/ld/testsuite/ld-elf/pr26936.d b/ld/testsuite/ld-elf/pr26936.d index 0a2831dd..344d5921 100644 --- a/ld/testsuite/ld-elf/pr26936.d +++ b/ld/testsuite/ld-elf/pr26936.d @@ -6,10 +6,10 @@ #readelf: -wL -W #target: [check_shared_lib_support] # Assembly source file for the HPPA assembler is renamed and modifed by -# sed. mn10300 and riscv put different numbers of local symbols in +# sed. loongarch and mn10300 and riscv put different numbers of local symbols in # linkonce section and comdat sections. xtensa has more than one member # in comdat groups. -#xfail: am33_2.0-*-* hppa*-*-hpux* mn10300-*-* riscv*-*-* xtensa*-*-* +#xfail: am33_2.0-*-* hppa*-*-hpux* loongarch*-*-* mn10300-*-* riscv*-*-* xtensa*-*-* #... CU: .*/pr26936c.s: diff --git a/ld/testsuite/ld-elf/shared.exp b/ld/testsuite/ld-elf/shared.exp index 8b7069c2..2da38504 100644 --- a/ld/testsuite/ld-elf/shared.exp +++ b/ld/testsuite/ld-elf/shared.exp @@ -502,7 +502,8 @@ run_ld_link_tests [list \ # but that is just an optimization so don't complain loudly. setup_xfail *-*-* clear_xfail alpha-*-* bfin-*-linux* csky-*-* frv-*-* hppa*-*-* i?86-*-* -clear_xfail ia64-*-* microblaze-*-* powerpc*-*-* x86_64-*-* xtensa-*-* +clear_xfail ia64-*-* loongarch*-*-* microblaze-*-* powerpc*-*-* x86_64-*-* +clear_xfail xtensa-*-* run_ld_link_tests { {"pr22374 function pointer initialization" "" "tmpdir/pr22374.so" "" "pr22374a.s" diff --git a/ld/testsuite/ld-loongarch-elf/64_pcrel.d b/ld/testsuite/ld-loongarch-elf/64_pcrel.d new file mode 100644 index 00000000..2ea063b7 --- /dev/null +++ b/ld/testsuite/ld-loongarch-elf/64_pcrel.d @@ -0,0 +1,4 @@ +#... +.*0xffffbffc.* +.*0xffffffff.* +#pass diff --git a/ld/testsuite/ld-loongarch-elf/64_pcrel.s b/ld/testsuite/ld-loongarch-elf/64_pcrel.s new file mode 100644 index 00000000..68af590f --- /dev/null +++ b/ld/testsuite/ld-loongarch-elf/64_pcrel.s @@ -0,0 +1,11 @@ +.text + nop + nop +L1: + nop +.data + nop + nop + .8byte 0x1234567812345678 + .reloc 0,R_LARCH_64_PCREL,L1 + nop diff --git a/ld/testsuite/ld-loongarch-elf/cmodel.exp b/ld/testsuite/ld-loongarch-elf/cmodel.exp index 7ef972a4..b428fd74 100644 --- a/ld/testsuite/ld-loongarch-elf/cmodel.exp +++ b/ld/testsuite/ld-loongarch-elf/cmodel.exp @@ -1,5 +1,5 @@ # Expect script for LoongArch ELF linker tests -# Copyright (C) 2022 Free Software Foundation, Inc. +# Copyright (C) 2022-2023 Free Software Foundation, Inc. # # This file is part of the GNU Binutils. # @@ -23,15 +23,18 @@ if ![istarget loongarch*-*-*] { return } -run_ld_link_tests [list \ - [list \ - "medium jirl plt" \ - "-shared" "" \ - "" \ - {libjirl.s} \ - [list \ - [list objdump -d cmodel-libjirl.dd] \ - ] \ - "libjirl.so" \ - ] \ - ] +if [check_shared_lib_support] { + run_ld_link_tests \ + [list \ + [list \ + "medium jirl plt" \ + "-shared" "" \ + "" \ + {libjirl.s} \ + [list \ + [list objdump -d cmodel-libjirl.dd] \ + ] \ + "libjirl.so" \ + ] \ + ] +} diff --git a/ld/testsuite/ld-loongarch-elf/disas-jirl-32.d b/ld/testsuite/ld-loongarch-elf/disas-jirl-32.d index 2f2a41af..cab7a5d4 100644 --- a/ld/testsuite/ld-loongarch-elf/disas-jirl-32.d +++ b/ld/testsuite/ld-loongarch-elf/disas-jirl-32.d @@ -10,6 +10,8 @@ Disassembly of section .text: 00000000.* <_start>: [ ]+0:[ ]+1a000014[ ]+pcalau12i[ ]+\$t8,[ ]+0 [ ]+0:[ ]+R_LARCH_PCALA_HI20[ ]+_start +[ ]+0:[ ]+R_LARCH_RELAX[ ]+\*ABS\* [ ]+4:[ ]+02800294[ ]+addi.w[ ]+\$t8,[ ]+\$t8,[ ]+0 [ ]+4:[ ]+R_LARCH_PCALA_LO12[ ]+_start +[ ]+4:[ ]+R_LARCH_RELAX[ ]+\*ABS\* [ ]+8:[ ]+4c000281[ ]+jirl[ ]+\$ra,[ ]+\$t8,[ ]+0 diff --git a/ld/testsuite/ld-loongarch-elf/disas-jirl.d b/ld/testsuite/ld-loongarch-elf/disas-jirl.d index 595c30c7..eeb8dd05 100644 --- a/ld/testsuite/ld-loongarch-elf/disas-jirl.d +++ b/ld/testsuite/ld-loongarch-elf/disas-jirl.d @@ -6,9 +6,11 @@ Disassembly of section .text: -00000000.*: +00000000.* <_start>: [ ]+0:[ ]+1a000014[ ]+pcalau12i[ ]+\$t8,[ ]+0 [ ]+0:[ ]+R_LARCH_PCALA_HI20[ ]+_start +[ ]+0:[ ]+R_LARCH_RELAX[ ]+\*ABS\* [ ]+4:[ ]+02c00294[ ]+addi.d[ ]+\$t8,[ ]+\$t8,[ ]+0 [ ]+4:[ ]+R_LARCH_PCALA_LO12[ ]+_start +[ ]+4:[ ]+R_LARCH_RELAX[ ]+\*ABS\* [ ]+8:[ ]+4c000281[ ]+jirl[ ]+\$ra,[ ]+\$t8,[ ]+0 diff --git a/ld/testsuite/ld-loongarch-elf/ifunc.exp b/ld/testsuite/ld-loongarch-elf/ifunc.exp index 2b55002f..d038113a 100644 --- a/ld/testsuite/ld-loongarch-elf/ifunc.exp +++ b/ld/testsuite/ld-loongarch-elf/ifunc.exp @@ -1,5 +1,5 @@ # Expect script for LoongArch assembler tests. -# Copyright (C) 2021-2022 Free Software Foundation, Inc. +# Copyright (C) 2021-2023 Free Software Foundation, Inc. # # This file is part of the GNU Binutils. # diff --git a/ld/testsuite/ld-loongarch-elf/jmp_op.d b/ld/testsuite/ld-loongarch-elf/jmp_op.d index 93452c31..231d7809 100644 --- a/ld/testsuite/ld-loongarch-elf/jmp_op.d +++ b/ld/testsuite/ld-loongarch-elf/jmp_op.d @@ -1,30 +1,50 @@ #as: -#objdump: -dr +#objdump: -dr -M no-aliases .*:[ ]+file format .* Disassembly of section .text: -00000000.* <.text>: +00000000.* <.L1>: [ ]+0:[ ]+03400000[ ]+andi[ ]+\$zero,[ ]+\$zero,[ ]+0x0 -[ ]+4:[ ]+63fffc04[ ]+bgtz[ ]+\$a0,[ ]+-4\(0x3fffc\)[ ]+#[ ]+0x0 -[ ]+8:[ ]+67fff880[ ]+bgez[ ]+\$a0,[ ]+-8\(0x3fff8\)[ ]+#[ ]+0x0 -[ ]+c:[ ]+67fff404[ ]+blez[ ]+\$a0,[ ]+-12\(0x3fff4\)[ ]+#[ ]+0x0 -[ ]+10:[ ]+43fff09f[ ]+beqz[ ]+\$a0,[ ]+-16\(0x7ffff0\)[ ]+#[ ]+0x0 -[ ]+14:[ ]+47ffec9f[ ]+bnez[ ]+\$a0,[ ]+-20\(0x7fffec\)[ ]+#[ ]+0x0 -[ ]+18:[ ]+4bffe81f[ ]+bceqz[ ]+\$fcc0,[ ]+-24\(0x7fffe8\)[ ]+#[ ]+0x0 -[ ]+1c:[ ]+4bffe51f[ ]+bcnez[ ]+\$fcc0,[ ]+-28\(0x7fffe4\)[ ]+#[ ]+0x0 +[ ]+4:[ ]+63fffc04[ ]+blt[ ]+\$zero,[ ]+\$a0,[ ]+-4[ ]+#[ ]+0[ ]+<.L1> +[ ]+4:[ ]+R_LARCH_B16[ ]+.L1 +[ ]+8:[ ]+67fff880[ ]+bge[ ]+\$a0,[ ]+\$zero,[ ]+-8[ ]+#[ ]+0[ ]+<.L1> +[ ]+8:[ ]+R_LARCH_B16[ ]+.L1 +[ ]+c:[ ]+67fff404[ ]+bge[ ]+\$zero,[ ]+\$a0,[ ]+-12[ ]+#[ ]+0[ ]+<.L1> +[ ]+c:[ ]+R_LARCH_B16[ ]+.L1 +[ ]+10:[ ]+43fff09f[ ]+beqz[ ]+\$a0,[ ]+-16[ ]+#[ ]+0[ ]+<.L1> +[ ]+10:[ ]+R_LARCH_B21[ ]+.L1 +[ ]+14:[ ]+47ffec9f[ ]+bnez[ ]+\$a0,[ ]+-20[ ]+#[ ]+0[ ]+<.L1> +[ ]+14:[ ]+R_LARCH_B21[ ]+.L1 +[ ]+18:[ ]+4bffe81f[ ]+bceqz[ ]+\$fcc0,[ ]+-24[ ]+#[ ]+0[ ]+<.L1> +[ ]+18:[ ]+R_LARCH_B21[ ]+.L1 +[ ]+1c:[ ]+4bffe51f[ ]+bcnez[ ]+\$fcc0,[ ]+-28[ ]+#[ ]+0[ ]+<.L1> +[ ]+1c:[ ]+R_LARCH_B21[ ]+.L1 [ ]+20:[ ]+4c000080[ ]+jirl[ ]+\$zero,[ ]+\$a0,[ ]+0 -[ ]+24:[ ]+53ffdfff[ ]+b[ ]+-36\(0xfffffdc\)[ ]+#[ ]+0x0 -[ ]+28:[ ]+57ffdbff[ ]+bl[ ]+-40\(0xfffffd8\)[ ]+#[ ]+0x0 -[ ]+2c:[ ]+5bffd485[ ]+beq[ ]+\$a0,[ ]+\$a1,[ ]+-44\(0x3ffd4\)[ ]+#[ ]+0x0 -[ ]+30:[ ]+5fffd085[ ]+bne[ ]+\$a0,[ ]+\$a1,[ ]+-48\(0x3ffd0\)[ ]+#[ ]+0x0 -[ ]+34:[ ]+63ffcc85[ ]+blt[ ]+\$a0,[ ]+\$a1,[ ]+-52\(0x3ffcc\)[ ]+#[ ]+0x0 -[ ]+38:[ ]+63ffc8a4[ ]+blt[ ]+\$a1,[ ]+\$a0,[ ]+-56\(0x3ffc8\)[ ]+#[ ]+0x0 -[ ]+3c:[ ]+67ffc485[ ]+bge[ ]+\$a0,[ ]+\$a1,[ ]+-60\(0x3ffc4\)[ ]+#[ ]+0x0 -[ ]+40:[ ]+67ffc0a4[ ]+bge[ ]+\$a1,[ ]+\$a0,[ ]+-64\(0x3ffc0\)[ ]+#[ ]+0x0 -[ ]+44:[ ]+6bffbc85[ ]+bltu[ ]+\$a0,[ ]+\$a1,[ ]+-68\(0x3ffbc\)[ ]+#[ ]+0x0 -[ ]+48:[ ]+6bffb8a4[ ]+bltu[ ]+\$a1,[ ]+\$a0,[ ]+-72\(0x3ffb8\)[ ]+#[ ]+0x0 -[ ]+4c:[ ]+6fffb485[ ]+bgeu[ ]+\$a0,[ ]+\$a1,[ ]+-76\(0x3ffb4\)[ ]+#[ ]+0x0 -[ ]+50:[ ]+6fffb0a4[ ]+bgeu[ ]+\$a1,[ ]+\$a0,[ ]+-80\(0x3ffb0\)[ ]+#[ ]+0x0 +[ ]+24:[ ]+53ffdfff[ ]+b[ ]+-36[ ]+#[ ]+0[ ]+<.L1> +[ ]+24:[ ]+R_LARCH_B26[ ]+.L1 +[ ]+28:[ ]+57ffdbff[ ]+bl[ ]+-40[ ]+#[ ]+0[ ]+<.L1> +[ ]+28:[ ]+R_LARCH_B26[ ]+.L1 +[ ]+2c:[ ]+5bffd485[ ]+beq[ ]+\$a0,[ ]+\$a1,[ ]+-44[ ]+#[ ]+0[ ]+<.L1> +[ ]+2c:[ ]+R_LARCH_B16[ ]+.L1 +[ ]+30:[ ]+5fffd085[ ]+bne[ ]+\$a0,[ ]+\$a1,[ ]+-48[ ]+#[ ]+0[ ]+<.L1> +[ ]+30:[ ]+R_LARCH_B16[ ]+.L1 +[ ]+34:[ ]+63ffcc85[ ]+blt[ ]+\$a0,[ ]+\$a1,[ ]+-52[ ]+#[ ]+0[ ]+<.L1> +[ ]+34:[ ]+R_LARCH_B16[ ]+.L1 +[ ]+38:[ ]+63ffc8a4[ ]+blt[ ]+\$a1,[ ]+\$a0,[ ]+-56[ ]+#[ ]+0[ ]+<.L1> +[ ]+38:[ ]+R_LARCH_B16[ ]+.L1 +[ ]+3c:[ ]+67ffc485[ ]+bge[ ]+\$a0,[ ]+\$a1,[ ]+-60[ ]+#[ ]+0[ ]+<.L1> +[ ]+3c:[ ]+R_LARCH_B16[ ]+.L1 +[ ]+40:[ ]+67ffc0a4[ ]+bge[ ]+\$a1,[ ]+\$a0,[ ]+-64[ ]+#[ ]+0[ ]+<.L1> +[ ]+40:[ ]+R_LARCH_B16[ ]+.L1 +[ ]+44:[ ]+6bffbc85[ ]+bltu[ ]+\$a0,[ ]+\$a1,[ ]+-68[ ]+#[ ]+0[ ]+<.L1> +[ ]+44:[ ]+R_LARCH_B16[ ]+.L1 +[ ]+48:[ ]+6bffb8a4[ ]+bltu[ ]+\$a1,[ ]+\$a0,[ ]+-72[ ]+#[ ]+0[ ]+<.L1> +[ ]+48:[ ]+R_LARCH_B16[ ]+.L1 +[ ]+4c:[ ]+6fffb485[ ]+bgeu[ ]+\$a0,[ ]+\$a1,[ ]+-76[ ]+#[ ]+0[ ]+<.L1> +[ ]+4c:[ ]+R_LARCH_B16[ ]+.L1 +[ ]+50:[ ]+6fffb0a4[ ]+bgeu[ ]+\$a1,[ ]+\$a0,[ ]+-80[ ]+#[ ]+0[ ]+<.L1> +[ ]+50:[ ]+R_LARCH_B16[ ]+.L1 +[ ]+54:[ ]+4c000020[ ]+jirl[ ]+\$zero,[ ]+\$ra,[ ]+0 diff --git a/ld/testsuite/ld-loongarch-elf/jmp_op.s b/ld/testsuite/ld-loongarch-elf/jmp_op.s index 1deb165a..56f98678 100644 --- a/ld/testsuite/ld-loongarch-elf/jmp_op.s +++ b/ld/testsuite/ld-loongarch-elf/jmp_op.s @@ -20,3 +20,4 @@ bltu $r4,$r5,.L1 bgtu $r4,$r5,.L1 bgeu $r4,$r5,.L1 bleu $r4,$r5,.L1 +ret diff --git a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp index 726ee823..b95cc53e 100644 --- a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp +++ b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp @@ -1,5 +1,5 @@ # Expect script for LoongArch ELF linker tests -# Copyright (C) 2021-2022 Free Software Foundation, Inc. +# Copyright (C) 2021-2023 Free Software Foundation, Inc. # # This file is part of the GNU Binutils. # @@ -40,3 +40,19 @@ if [istarget "loongarch32-*-*"] { run_dump_test "syscall" run_dump_test "disas-jirl-32" } + +if [istarget "loongarch64-*-*"] { + run_ld_link_tests \ + [list \ + [list \ + "64_pcrel" \ + "-e 0x0 -z relro" "" \ + "" \ + {64_pcrel.s} \ + [list \ + [list objdump -D 64_pcrel.d] \ + ] \ + "64_pcrel" \ + ] \ + ] +} diff --git a/ld/testsuite/ld-loongarch-elf/local-ifunc-reloc.d b/ld/testsuite/ld-loongarch-elf/local-ifunc-reloc.d index 29f2d3f3..6bcd87f6 100644 --- a/ld/testsuite/ld-loongarch-elf/local-ifunc-reloc.d +++ b/ld/testsuite/ld-loongarch-elf/local-ifunc-reloc.d @@ -5,6 +5,6 @@ .*: +file format .* DYNAMIC RELOCATION RECORDS -OFFSET +TYPE +VALUE -[[:xdigit:]]+ R_LARCH_IRELATIVE +\*ABS\*\+0x[[:xdigit:]]+ +OFFSET +TYPE +VALUE [[:xdigit:]]+ R_LARCH_64 +test +[[:xdigit:]]+ R_LARCH_IRELATIVE +\*ABS\*\+0x[[:xdigit:]]+ diff --git a/ld/testsuite/ld-loongarch-elf/macro_op.d b/ld/testsuite/ld-loongarch-elf/macro_op.d index a1c64fcf..edc71bc0 100644 --- a/ld/testsuite/ld-loongarch-elf/macro_op.d +++ b/ld/testsuite/ld-loongarch-elf/macro_op.d @@ -6,118 +6,150 @@ Disassembly of section .text: -00000000.* <.text>: +00000000.* <.L1>: [ ]+0:[ ]+00150004[ ]+move[ ]+\$a0,[ ]+\$zero -[ ]+4:[ ]+02bffc04[ ]+addi.w[ ]+\$a0,[ ]+\$zero,[ ]+-1\(0xfff\) +[ ]+4:[ ]+02bffc04[ ]+li\.w[ ]+\$a0,[ ]+-1 [ ]+8:[ ]+00150004[ ]+move[ ]+\$a0,[ ]+\$zero -[ ]+c:[ ]+02bffc04[ ]+addi.w[ ]+\$a0,[ ]+\$zero,[ ]+-1\(0xfff\) +[ ]+c:[ ]+02bffc04[ ]+li\.w[ ]+\$a0,[ ]+-1 [ ]+10:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 -[ ]+10:[ ]+R_LARCH_GOT_PC_HI20[ ]+.text +[ ]+10:[ ]+R_LARCH_GOT_PC_HI20[ ]+.L1 +[ ]+10:[ ]+R_LARCH_RELAX[ ]+\*ABS\* [ ]+14:[ ]+28c00084[ ]+ld.d[ ]+\$a0,[ ]+\$a0,[ ]+0 -[ ]+14:[ ]+R_LARCH_GOT_PC_LO12[ ]+.text +[ ]+14:[ ]+R_LARCH_GOT_PC_LO12[ ]+.L1 +[ ]+14:[ ]+R_LARCH_RELAX[ ]+\*ABS\* [ ]+18:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 -[ ]+18:[ ]+R_LARCH_GOT_PC_HI20[ ]+.text +[ ]+18:[ ]+R_LARCH_GOT_PC_HI20[ ]+.L1 +[ ]+18:[ ]+R_LARCH_RELAX[ ]+\*ABS\* [ ]+1c:[ ]+28c00084[ ]+ld.d[ ]+\$a0,[ ]+\$a0,[ ]+0 -[ ]+1c:[ ]+R_LARCH_GOT_PC_LO12[ ]+.text +[ ]+1c:[ ]+R_LARCH_GOT_PC_LO12[ ]+.L1 +[ ]+1c:[ ]+R_LARCH_RELAX[ ]+\*ABS\* [ ]+20:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 -[ ]+20:[ ]+R_LARCH_GOT_PC_HI20[ ]+.text -[ ]+24:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0 -[ ]+24:[ ]+R_LARCH_GOT_PC_LO12[ ]+.text +[ ]+20:[ ]+R_LARCH_GOT_PC_HI20[ ]+.L1 +[ ]+20:[ ]+R_LARCH_RELAX[ ]+\*ABS\* +[ ]+24:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0 +[ ]+24:[ ]+R_LARCH_GOT_PC_LO12[ ]+.L1 +[ ]+24:[ ]+R_LARCH_RELAX[ ]+\*ABS\* [ ]+28:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0 -[ ]+28:[ ]+R_LARCH_GOT64_PC_LO20[ ]+.text +[ ]+28:[ ]+R_LARCH_GOT64_PC_LO20[ ]+.L1 [ ]+2c:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1,[ ]+\$a1,[ ]+0 -[ ]+2c:[ ]+R_LARCH_GOT64_PC_HI12[ ]+.text +[ ]+2c:[ ]+R_LARCH_GOT64_PC_HI12[ ]+.L1 [ ]+30:[ ]+380c1484[ ]+ldx.d[ ]+\$a0,[ ]+\$a0,[ ]+\$a1 [ ]+34:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 -[ ]+34:[ ]+R_LARCH_GOT_PC_HI20[ ]+.text +[ ]+34:[ ]+R_LARCH_GOT_PC_HI20[ ]+.L1 +[ ]+34:[ ]+R_LARCH_RELAX[ ]+\*ABS\* [ ]+38:[ ]+28c00084[ ]+ld.d[ ]+\$a0,[ ]+\$a0,[ ]+0 -[ ]+38:[ ]+R_LARCH_GOT_PC_LO12[ ]+.text +[ ]+38:[ ]+R_LARCH_GOT_PC_LO12[ ]+.L1 +[ ]+38:[ ]+R_LARCH_RELAX[ ]+\*ABS\* [ ]+3c:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 -[ ]+3c:[ ]+R_LARCH_GOT_PC_HI20[ ]+.text -[ ]+40:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0 -[ ]+40:[ ]+R_LARCH_GOT_PC_LO12[ ]+.text +[ ]+3c:[ ]+R_LARCH_GOT_PC_HI20[ ]+.L1 +[ ]+3c:[ ]+R_LARCH_RELAX[ ]+\*ABS\* +[ ]+40:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0 +[ ]+40:[ ]+R_LARCH_GOT_PC_LO12[ ]+.L1 +[ ]+40:[ ]+R_LARCH_RELAX[ ]+\*ABS\* [ ]+44:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0 -[ ]+44:[ ]+R_LARCH_GOT64_PC_LO20[ ]+.text +[ ]+44:[ ]+R_LARCH_GOT64_PC_LO20[ ]+.L1 [ ]+48:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1,[ ]+\$a1,[ ]+0 -[ ]+48:[ ]+R_LARCH_GOT64_PC_HI12[ ]+.text +[ ]+48:[ ]+R_LARCH_GOT64_PC_HI12[ ]+.L1 [ ]+4c:[ ]+380c1484[ ]+ldx.d[ ]+\$a0,[ ]+\$a0,[ ]+\$a1 [ ]+50:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 -[ ]+50:[ ]+R_LARCH_GOT_PC_HI20[ ]+.text +[ ]+50:[ ]+R_LARCH_GOT_PC_HI20[ ]+.L1 +[ ]+50:[ ]+R_LARCH_RELAX[ ]+\*ABS\* [ ]+54:[ ]+28c00084[ ]+ld.d[ ]+\$a0,[ ]+\$a0,[ ]+0 -[ ]+54:[ ]+R_LARCH_GOT_PC_LO12[ ]+.text +[ ]+54:[ ]+R_LARCH_GOT_PC_LO12[ ]+.L1 +[ ]+54:[ ]+R_LARCH_RELAX[ ]+\*ABS\* [ ]+58:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 -[ ]+58:[ ]+R_LARCH_GOT_PC_HI20[ ]+.text -[ ]+5c:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0 -[ ]+5c:[ ]+R_LARCH_GOT_PC_LO12[ ]+.text +[ ]+58:[ ]+R_LARCH_GOT_PC_HI20[ ]+.L1 +[ ]+58:[ ]+R_LARCH_RELAX[ ]+\*ABS\* +[ ]+5c:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0 +[ ]+5c:[ ]+R_LARCH_GOT_PC_LO12[ ]+.L1 +[ ]+5c:[ ]+R_LARCH_RELAX[ ]+\*ABS\* [ ]+60:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0 -[ ]+60:[ ]+R_LARCH_GOT64_PC_LO20[ ]+.text +[ ]+60:[ ]+R_LARCH_GOT64_PC_LO20[ ]+.L1 [ ]+64:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1,[ ]+\$a1,[ ]+0 -[ ]+64:[ ]+R_LARCH_GOT64_PC_HI12[ ]+.text +[ ]+64:[ ]+R_LARCH_GOT64_PC_HI12[ ]+.L1 [ ]+68:[ ]+380c1484[ ]+ldx.d[ ]+\$a0,[ ]+\$a0,[ ]+\$a1 [ ]+6c:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 -[ ]+6c:[ ]+R_LARCH_PCALA_HI20[ ]+.text +[ ]+6c:[ ]+R_LARCH_PCALA_HI20[ ]+.L1 +[ ]+6c:[ ]+R_LARCH_RELAX[ ]+\*ABS\* [ ]+70:[ ]+02c00084[ ]+addi.d[ ]+\$a0,[ ]+\$a0,[ ]+0 -[ ]+70:[ ]+R_LARCH_PCALA_LO12[ ]+.text +[ ]+70:[ ]+R_LARCH_PCALA_LO12[ ]+.L1 +[ ]+70:[ ]+R_LARCH_RELAX[ ]+\*ABS\* [ ]+74:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 -[ ]+74:[ ]+R_LARCH_PCALA_HI20[ ]+.text -[ ]+78:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0 -[ ]+78:[ ]+R_LARCH_PCALA_LO12[ ]+.text +[ ]+74:[ ]+R_LARCH_PCALA_HI20[ ]+.L1 +[ ]+74:[ ]+R_LARCH_RELAX[ ]+\*ABS\* +[ ]+78:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0 +[ ]+78:[ ]+R_LARCH_PCALA_LO12[ ]+.L1 +[ ]+78:[ ]+R_LARCH_RELAX[ ]+\*ABS\* [ ]+7c:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0 -[ ]+7c:[ ]+R_LARCH_PCALA64_LO20[ ]+.text +[ ]+7c:[ ]+R_LARCH_PCALA64_LO20[ ]+.L1 [ ]+80:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1,[ ]+\$a1,[ ]+0 -[ ]+80:[ ]+R_LARCH_PCALA64_HI12[ ]+.text +[ ]+80:[ ]+R_LARCH_PCALA64_HI12[ ]+.L1 [ ]+84:[ ]+00109484[ ]+add.d[ ]+\$a0,[ ]+\$a0,[ ]+\$a1 [ ]+88:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 -[ ]+88:[ ]+R_LARCH_PCALA_HI20[ ]+.text +[ ]+88:[ ]+R_LARCH_PCALA_HI20[ ]+.L1 +[ ]+88:[ ]+R_LARCH_RELAX[ ]+\*ABS\* [ ]+8c:[ ]+02c00084[ ]+addi.d[ ]+\$a0,[ ]+\$a0,[ ]+0 -[ ]+8c:[ ]+R_LARCH_PCALA_LO12[ ]+.text +[ ]+8c:[ ]+R_LARCH_PCALA_LO12[ ]+.L1 +[ ]+8c:[ ]+R_LARCH_RELAX[ ]+\*ABS\* [ ]+90:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 -[ ]+90:[ ]+R_LARCH_PCALA_HI20[ ]+.text -[ ]+94:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0 -[ ]+94:[ ]+R_LARCH_PCALA_LO12[ ]+.text +[ ]+90:[ ]+R_LARCH_PCALA_HI20[ ]+.L1 +[ ]+90:[ ]+R_LARCH_RELAX[ ]+\*ABS\* +[ ]+94:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0 +[ ]+94:[ ]+R_LARCH_PCALA_LO12[ ]+.L1 +[ ]+94:[ ]+R_LARCH_RELAX[ ]+\*ABS\* [ ]+98:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0 -[ ]+98:[ ]+R_LARCH_PCALA64_LO20[ ]+.text +[ ]+98:[ ]+R_LARCH_PCALA64_LO20[ ]+.L1 [ ]+9c:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1,[ ]+\$a1,[ ]+0 -[ ]+9c:[ ]+R_LARCH_PCALA64_HI12[ ]+.text +[ ]+9c:[ ]+R_LARCH_PCALA64_HI12[ ]+.L1 [ ]+a0:[ ]+00109484[ ]+add.d[ ]+\$a0,[ ]+\$a0,[ ]+\$a1 [ ]+a4:[ ]+14000004[ ]+lu12i.w[ ]+\$a0,[ ]+0 [ ]+a4:[ ]+R_LARCH_MARK_LA[ ]+\*ABS\* -[ ]+a4:[ ]+R_LARCH_ABS_HI20[ ]+.text +[ ]+a4:[ ]+R_LARCH_ABS_HI20[ ]+.L1 [ ]+a8:[ ]+03800084[ ]+ori[ ]+\$a0,[ ]+\$a0,[ ]+0x0 -[ ]+a8:[ ]+R_LARCH_ABS_LO12[ ]+.text +[ ]+a8:[ ]+R_LARCH_ABS_LO12[ ]+.L1 [ ]+ac:[ ]+16000004[ ]+lu32i.d[ ]+\$a0,[ ]+0 -[ ]+ac:[ ]+R_LARCH_ABS64_LO20[ ]+.text +[ ]+ac:[ ]+R_LARCH_ABS64_LO20[ ]+.L1 [ ]+b0:[ ]+03000084[ ]+lu52i.d[ ]+\$a0,[ ]+\$a0,[ ]+0 -[ ]+b0:[ ]+R_LARCH_ABS64_HI12[ ]+.text +[ ]+b0:[ ]+R_LARCH_ABS64_HI12[ ]+.L1 [ ]+b4:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 -[ ]+b4:[ ]+R_LARCH_PCALA_HI20[ ]+.text +[ ]+b4:[ ]+R_LARCH_PCALA_HI20[ ]+.L1 +[ ]+b4:[ ]+R_LARCH_RELAX[ ]+\*ABS\* [ ]+b8:[ ]+02c00084[ ]+addi.d[ ]+\$a0,[ ]+\$a0,[ ]+0 -[ ]+b8:[ ]+R_LARCH_PCALA_LO12[ ]+.text +[ ]+b8:[ ]+R_LARCH_PCALA_LO12[ ]+.L1 +[ ]+b8:[ ]+R_LARCH_RELAX[ ]+\*ABS\* [ ]+bc:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 -[ ]+bc:[ ]+R_LARCH_PCALA_HI20[ ]+.text +[ ]+bc:[ ]+R_LARCH_PCALA_HI20[ ]+.L1 +[ ]+bc:[ ]+R_LARCH_RELAX[ ]+\*ABS\* [ ]+c0:[ ]+02c00084[ ]+addi.d[ ]+\$a0,[ ]+\$a0,[ ]+0 -[ ]+c0:[ ]+R_LARCH_PCALA_LO12[ ]+.text +[ ]+c0:[ ]+R_LARCH_PCALA_LO12[ ]+.L1 +[ ]+c0:[ ]+R_LARCH_RELAX[ ]+\*ABS\* [ ]+c4:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 -[ ]+c4:[ ]+R_LARCH_PCALA_HI20[ ]+.text -[ ]+c8:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0 -[ ]+c8:[ ]+R_LARCH_PCALA_LO12[ ]+.text +[ ]+c4:[ ]+R_LARCH_PCALA_HI20[ ]+.L1 +[ ]+c4:[ ]+R_LARCH_RELAX[ ]+\*ABS\* +[ ]+c8:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0 +[ ]+c8:[ ]+R_LARCH_PCALA_LO12[ ]+.L1 +[ ]+c8:[ ]+R_LARCH_RELAX[ ]+\*ABS\* [ ]+cc:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0 -[ ]+cc:[ ]+R_LARCH_PCALA64_LO20[ ]+.text +[ ]+cc:[ ]+R_LARCH_PCALA64_LO20[ ]+.L1 [ ]+d0:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1,[ ]+\$a1,[ ]+0 -[ ]+d0:[ ]+R_LARCH_PCALA64_HI12[ ]+.text +[ ]+d0:[ ]+R_LARCH_PCALA64_HI12[ ]+.L1 [ ]+d4:[ ]+00109484[ ]+add.d[ ]+\$a0,[ ]+\$a0,[ ]+\$a1 [ ]+d8:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 -[ ]+d8:[ ]+R_LARCH_GOT_PC_HI20[ ]+.text +[ ]+d8:[ ]+R_LARCH_GOT_PC_HI20[ ]+.L1 +[ ]+d8:[ ]+R_LARCH_RELAX[ ]+\*ABS\* [ ]+dc:[ ]+28c00084[ ]+ld.d[ ]+\$a0,[ ]+\$a0,[ ]+0 -[ ]+dc:[ ]+R_LARCH_GOT_PC_LO12[ ]+.text +[ ]+dc:[ ]+R_LARCH_GOT_PC_LO12[ ]+.L1 +[ ]+dc:[ ]+R_LARCH_RELAX[ ]+\*ABS\* [ ]+e0:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 -[ ]+e0:[ ]+R_LARCH_GOT_PC_HI20[ ]+.text -[ ]+e4:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0 -[ ]+e4:[ ]+R_LARCH_GOT_PC_LO12[ ]+.text +[ ]+e0:[ ]+R_LARCH_GOT_PC_HI20[ ]+.L1 +[ ]+e0:[ ]+R_LARCH_RELAX[ ]+\*ABS\* +[ ]+e4:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0 +[ ]+e4:[ ]+R_LARCH_GOT_PC_LO12[ ]+.L1 +[ ]+e4:[ ]+R_LARCH_RELAX[ ]+\*ABS\* [ ]+e8:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0 -[ ]+e8:[ ]+R_LARCH_GOT64_PC_LO20[ ]+.text +[ ]+e8:[ ]+R_LARCH_GOT64_PC_LO20[ ]+.L1 [ ]+ec:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1,[ ]+\$a1,[ ]+0 -[ ]+ec:[ ]+R_LARCH_GOT64_PC_HI12[ ]+.text +[ ]+ec:[ ]+R_LARCH_GOT64_PC_HI12[ ]+.L1 [ ]+f0:[ ]+380c1484[ ]+ldx.d[ ]+\$a0,[ ]+\$a0,[ ]+\$a1 [ ]+f4:[ ]+14000004[ ]+lu12i.w[ ]+\$a0,[ ]+0 [ ]+f4:[ ]+R_LARCH_TLS_LE_HI20[ ]+TLS1 @@ -129,7 +161,7 @@ Disassembly of section .text: [ ]+100:[ ]+R_LARCH_TLS_IE_PC_LO12[ ]+TLS1 [ ]+104:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 [ ]+104:[ ]+R_LARCH_TLS_IE_PC_HI20[ ]+TLS1 -[ ]+108:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0 +[ ]+108:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0 [ ]+108:[ ]+R_LARCH_TLS_IE_PC_LO12[ ]+TLS1 [ ]+10c:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0 [ ]+10c:[ ]+R_LARCH_TLS_IE64_PC_LO20[ ]+TLS1 @@ -140,10 +172,12 @@ Disassembly of section .text: [ ]+118:[ ]+R_LARCH_TLS_LD_PC_HI20[ ]+TLS1 [ ]+11c:[ ]+02c00084[ ]+addi.d[ ]+\$a0,[ ]+\$a0,[ ]+0 [ ]+11c:[ ]+R_LARCH_GOT_PC_LO12[ ]+TLS1 +[ ]+11c:[ ]+R_LARCH_RELAX[ ]+\*ABS\* [ ]+120:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 [ ]+120:[ ]+R_LARCH_TLS_LD_PC_HI20[ ]+TLS1 -[ ]+124:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0 +[ ]+124:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0 [ ]+124:[ ]+R_LARCH_GOT_PC_LO12[ ]+TLS1 +[ ]+124:[ ]+R_LARCH_RELAX[ ]+\*ABS\* [ ]+128:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0 [ ]+128:[ ]+R_LARCH_GOT64_PC_LO20[ ]+TLS1 [ ]+12c:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1,[ ]+\$a1,[ ]+0 @@ -153,10 +187,12 @@ Disassembly of section .text: [ ]+134:[ ]+R_LARCH_TLS_GD_PC_HI20[ ]+TLS1 [ ]+138:[ ]+02c00084[ ]+addi.d[ ]+\$a0,[ ]+\$a0,[ ]+0 [ ]+138:[ ]+R_LARCH_GOT_PC_LO12[ ]+TLS1 +[ ]+138:[ ]+R_LARCH_RELAX[ ]+\*ABS\* [ ]+13c:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 [ ]+13c:[ ]+R_LARCH_TLS_GD_PC_HI20[ ]+TLS1 -[ ]+140:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0 +[ ]+140:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0 [ ]+140:[ ]+R_LARCH_GOT_PC_LO12[ ]+TLS1 +[ ]+140:[ ]+R_LARCH_RELAX[ ]+\*ABS\* [ ]+144:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0 [ ]+144:[ ]+R_LARCH_GOT64_PC_LO20[ ]+TLS1 [ ]+148:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1,[ ]+\$a1,[ ]+0 diff --git a/ld/testsuite/ld-loongarch-elf/macro_op_32.d b/ld/testsuite/ld-loongarch-elf/macro_op_32.d index 145d852b..188026a5 100644 --- a/ld/testsuite/ld-loongarch-elf/macro_op_32.d +++ b/ld/testsuite/ld-loongarch-elf/macro_op_32.d @@ -7,36 +7,46 @@ Disassembly of section .text: -00000000.* <.text>: +00000000.* <.L1>: [ ]+0:[ ]+00150004[ ]+move[ ]+\$a0,[ ]+\$zero -[ ]+4:[ ]+02bffc04[ ]+addi.w[ ]+\$a0,[ ]+\$zero,[ ]+-1\(0xfff\) +[ ]+4:[ ]+02bffc04[ ]+li\.w[ ]+\$a0,[ ]+-1 [ ]+8:[ ]+00150004[ ]+move[ ]+\$a0,[ ]+\$zero -[ ]+c:[ ]+02bffc04[ ]+addi.w[ ]+\$a0,[ ]+\$zero,[ ]+-1\(0xfff\) +[ ]+c:[ ]+02bffc04[ ]+li\.w[ ]+\$a0,[ ]+-1 [ ]+10:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 -[ ]+10:[ ]+R_LARCH_GOT_PC_HI20[ ]+.text +[ ]+10:[ ]+R_LARCH_GOT_PC_HI20[ ]+.L1 +[ ]+10:[ ]+R_LARCH_RELAX[ ]+\*ABS\* [ ]+14:[ ]+28800084[ ]+ld.w[ ]+\$a0,[ ]+\$a0,[ ]+0 -[ ]+14:[ ]+R_LARCH_GOT_PC_LO12[ ]+.text +[ ]+14:[ ]+R_LARCH_GOT_PC_LO12[ ]+.L1 +[ ]+14:[ ]+R_LARCH_RELAX[ ]+\*ABS\* [ ]+18:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 -[ ]+18:[ ]+R_LARCH_GOT_PC_HI20[ ]+.text +[ ]+18:[ ]+R_LARCH_GOT_PC_HI20[ ]+.L1 +[ ]+18:[ ]+R_LARCH_RELAX[ ]+\*ABS\* [ ]+1c:[ ]+28800084[ ]+ld.w[ ]+\$a0,[ ]+\$a0,[ ]+0 -[ ]+1c:[ ]+R_LARCH_GOT_PC_LO12[ ]+.text +[ ]+1c:[ ]+R_LARCH_GOT_PC_LO12[ ]+.L1 +[ ]+1c:[ ]+R_LARCH_RELAX[ ]+\*ABS\* [ ]+20:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 -[ ]+20:[ ]+R_LARCH_PCALA_HI20[ ]+.text +[ ]+20:[ ]+R_LARCH_PCALA_HI20[ ]+.L1 +[ ]+20:[ ]+R_LARCH_RELAX[ ]+\*ABS\* [ ]+24:[ ]+02800084[ ]+addi.w[ ]+\$a0,[ ]+\$a0,[ ]+0 -[ ]+24:[ ]+R_LARCH_PCALA_LO12[ ]+.text +[ ]+24:[ ]+R_LARCH_PCALA_LO12[ ]+.L1 +[ ]+24:[ ]+R_LARCH_RELAX[ ]+\*ABS\* [ ]+28:[ ]+14000004[ ]+lu12i.w[ ]+\$a0,[ ]+0 [ ]+28:[ ]+R_LARCH_MARK_LA[ ]+\*ABS\* -[ ]+28:[ ]+R_LARCH_ABS_HI20[ ]+.text +[ ]+28:[ ]+R_LARCH_ABS_HI20[ ]+.L1 [ ]+2c:[ ]+03800084[ ]+ori[ ]+\$a0,[ ]+\$a0,[ ]+0x0 -[ ]+2c:[ ]+R_LARCH_ABS_LO12[ ]+.text +[ ]+2c:[ ]+R_LARCH_ABS_LO12[ ]+.L1 [ ]+30:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 -[ ]+30:[ ]+R_LARCH_PCALA_HI20[ ]+.text +[ ]+30:[ ]+R_LARCH_PCALA_HI20[ ]+.L1 +[ ]+30:[ ]+R_LARCH_RELAX[ ]+\*ABS\* [ ]+34:[ ]+02800084[ ]+addi.w[ ]+\$a0,[ ]+\$a0,[ ]+0 -[ ]+34:[ ]+R_LARCH_PCALA_LO12[ ]+.text +[ ]+34:[ ]+R_LARCH_PCALA_LO12[ ]+.L1 +[ ]+34:[ ]+R_LARCH_RELAX[ ]+\*ABS\* [ ]+38:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 -[ ]+38:[ ]+R_LARCH_GOT_PC_HI20[ ]+.text +[ ]+38:[ ]+R_LARCH_GOT_PC_HI20[ ]+.L1 +[ ]+38:[ ]+R_LARCH_RELAX[ ]+\*ABS\* [ ]+3c:[ ]+28800084[ ]+ld.w[ ]+\$a0,[ ]+\$a0,[ ]+0 -[ ]+3c:[ ]+R_LARCH_GOT_PC_LO12[ ]+.text +[ ]+3c:[ ]+R_LARCH_GOT_PC_LO12[ ]+.L1 +[ ]+3c:[ ]+R_LARCH_RELAX[ ]+\*ABS\* [ ]+40:[ ]+14000004[ ]+lu12i.w[ ]+\$a0,[ ]+0 [ ]+40:[ ]+R_LARCH_TLS_LE_HI20[ ]+TLS1 [ ]+44:[ ]+03800084[ ]+ori[ ]+\$a0,[ ]+\$a0,[ ]+0x0 @@ -49,7 +59,9 @@ Disassembly of section .text: [ ]+50:[ ]+R_LARCH_TLS_LD_PC_HI20[ ]+TLS1 [ ]+54:[ ]+02800084[ ]+addi.w[ ]+\$a0,[ ]+\$a0,[ ]+0 [ ]+54:[ ]+R_LARCH_GOT_PC_LO12[ ]+TLS1 +[ ]+54:[ ]+R_LARCH_RELAX[ ]+\*ABS\* [ ]+58:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 [ ]+58:[ ]+R_LARCH_TLS_GD_PC_HI20[ ]+TLS1 [ ]+5c:[ ]+02800084[ ]+addi.w[ ]+\$a0,[ ]+\$a0,[ ]+0 [ ]+5c:[ ]+R_LARCH_GOT_PC_LO12[ ]+TLS1 +[ ]+5c:[ ]+R_LARCH_RELAX[ ]+\*ABS\* diff --git a/ld/testsuite/ld-loongarch-elf/pic.exp b/ld/testsuite/ld-loongarch-elf/pic.exp index 40a5138a..2ca5b3a0 100644 --- a/ld/testsuite/ld-loongarch-elf/pic.exp +++ b/ld/testsuite/ld-loongarch-elf/pic.exp @@ -1,5 +1,5 @@ # Expect script for LoongArch ELF linker tests -# Copyright (C) 2022 Free Software Foundation, Inc. +# Copyright (C) 2022-2023 Free Software Foundation, Inc. # # This file is part of the GNU Binutils. # diff --git a/ld/testsuite/ld-loongarch-elf/relax-align.dd b/ld/testsuite/ld-loongarch-elf/relax-align.dd new file mode 100644 index 00000000..5fce2255 --- /dev/null +++ b/ld/testsuite/ld-loongarch-elf/relax-align.dd @@ -0,0 +1,7 @@ +#... +.*pcaddi.* +.*pcaddi.* +.*nop.* +.*nop.* +.*0:.*pcaddi.* +#pass diff --git a/ld/testsuite/ld-loongarch-elf/relax-align.s b/ld/testsuite/ld-loongarch-elf/relax-align.s new file mode 100644 index 00000000..9617c02d --- /dev/null +++ b/ld/testsuite/ld-loongarch-elf/relax-align.s @@ -0,0 +1,9 @@ +# relax-align.o has 3 andi(nop) insns. +# relax-align has 2 andi insns, ld relax delete andi insns. +# the last pcaddi 16 bytes align. + .text +L1: + la.local $a0, L1 + la.local $a0, L1 + .align 4 + la.local $a0, L1 diff --git a/ld/testsuite/ld-loongarch-elf/relax.exp b/ld/testsuite/ld-loongarch-elf/relax.exp new file mode 100644 index 00000000..7ff876d7 --- /dev/null +++ b/ld/testsuite/ld-loongarch-elf/relax.exp @@ -0,0 +1,77 @@ +# Expect script for LoongArch ELF linker tests +# Copyright (C) 2022 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, +# MA 02110-1301, USA. +# + +if [istarget loongarch64-*-*] { + + if [isbuild loongarch64-*-*] { + set testname "loongarch relax build" + set pre_builds [list \ + [list \ + "$testname" \ + "" \ + "" \ + {relax.s} \ + {} \ + "relax" \ + ] \ + ] + + run_cc_link_tests $pre_builds + + if [file exist "tmpdir/relax"] { + set objdump_output [run_host_cmd "objdump" "-d tmpdir/relax"] + if { [ regexp ".*pcaddi.*pcaddi.*" $objdump_output] } { + pass "loongarch relax" + } { + fail "loongarch relax" + } + } + } + + run_ld_link_tests \ + [list \ + [list \ + "relax-align" \ + "-e 0x0 -z relro" "" \ + "" \ + {relax-align.s} \ + [list \ + [list objdump -d relax-align.dd] \ + ] \ + "relax-align" \ + ] \ + ] + + set objdump_flags "-s -j .data" + run_ld_link_tests \ + [list \ + [list \ + "uleb128" \ + "-e 0x0" "" \ + "" \ + {uleb128.s} \ + [list \ + [list objdump $objdump_flags uleb128.dd] \ + ] \ + "uleb128" \ + ] \ + ] +} diff --git a/ld/testsuite/ld-loongarch-elf/relax.s b/ld/testsuite/ld-loongarch-elf/relax.s new file mode 100644 index 00000000..2979ffa3 --- /dev/null +++ b/ld/testsuite/ld-loongarch-elf/relax.s @@ -0,0 +1,16 @@ + .data + .global a + .type a, @object +a: + .word 123 + + .text + .global main + .type main, @function +main: + la.local $a0, a + ld.w $a1, $a0, 0 + la.global $a0, a + ld.w $a0, $a0, 0 + sub.d $a0, $a0, $a1 + jr $ra diff --git a/ld/testsuite/ld-loongarch-elf/uleb128.dd b/ld/testsuite/ld-loongarch-elf/uleb128.dd new file mode 100644 index 00000000..c4ad3070 --- /dev/null +++ b/ld/testsuite/ld-loongarch-elf/uleb128.dd @@ -0,0 +1,10 @@ +.*: .* + +Contents of section .* + [0-9a-f]+ 01020381 01000000 00000000 00000000.* +#... + [0-9a-f]+ 00000004 ffff0500 06078380 01000000.* +#... + [0-9a-f]+ 00000000 00000000 00000008 ffffffff.* + [0-9a-f]+ 09090909 09090909 09090909 09090909.* +#pass diff --git a/ld/testsuite/ld-loongarch-elf/uleb128.s b/ld/testsuite/ld-loongarch-elf/uleb128.s new file mode 100644 index 00000000..7299fb91 --- /dev/null +++ b/ld/testsuite/ld-loongarch-elf/uleb128.s @@ -0,0 +1,21 @@ +# From gas/all/relax.s, test ld process add_uleb128/sub_uleb128 reloc pair. + .data + .byte 1, 2, 3 + .uleb128 L2 - L1 +L1: + .space 128 - 2 + .byte 4 + .p2align 1, 0xff +L2: + .byte 5 + + .p2align 2 + .byte 6, 7 + .uleb128 L4 - L3 +L3: + .space 128*128 - 2 + .byte 8 + .p2align 2, 0xff +L4: + .byte 9 + .p2align 4, 9 diff --git a/opcodes/loongarch-dis.c b/opcodes/loongarch-dis.c index 9dcf989d..d15848fc 100644 --- a/opcodes/loongarch-dis.c +++ b/opcodes/loongarch-dis.c @@ -25,6 +25,15 @@ #include "libiberty.h" #include <stdlib.h> +static bool loongarch_dis_show_aliases = true; +static const char *const *loongarch_r_disname = NULL; +static const char *const *loongarch_f_disname = NULL; +static const char *const *loongarch_fc_disname = NULL; +static const char *const *loongarch_c_disname = NULL; +static const char *const *loongarch_cr_disname = NULL; +static const char *const *loongarch_v_disname = NULL; +static const char *const *loongarch_x_disname = NULL; + static const struct loongarch_opcode * get_loongarch_opcode_by_binfmt (insn_t insn) { @@ -41,7 +50,9 @@ get_loongarch_opcode_by_binfmt (insn_t insn) { for (it = ase->opcodes; it->mask; it++) if (!ase->opc_htab[LARCH_INSN_OPC (it->match)] - && it->macro == NULL) + && it->macro == NULL + && (!(it->pinfo & INSN_DIS_ALIAS) + || loongarch_dis_show_aliases)) ase->opc_htab[LARCH_INSN_OPC (it->match)] = it; for (i = 0; i < 16; i++) if (!ase->opc_htab[i]) @@ -59,13 +70,6 @@ get_loongarch_opcode_by_binfmt (insn_t insn) return NULL; } -static const char *const *loongarch_r_disname = NULL; -static const char *const *loongarch_f_disname = NULL; -static const char *const *loongarch_c_disname = NULL; -static const char *const *loongarch_cr_disname = NULL; -static const char *const *loongarch_v_disname = NULL; -static const char *const *loongarch_x_disname = NULL; - static void set_default_loongarch_dis_options (void) { @@ -75,9 +79,12 @@ set_default_loongarch_dis_options (void) LARCH_opts.ase_df = 1; LARCH_opts.ase_lsx = 1; LARCH_opts.ase_lasx = 1; + LARCH_opts.ase_lvz = 1; + LARCH_opts.ase_lbt = 1; loongarch_r_disname = loongarch_r_lp64_name; loongarch_f_disname = loongarch_f_lp64_name; + loongarch_fc_disname = loongarch_fc_normal_name; loongarch_c_disname = loongarch_c_normal_name; loongarch_cr_disname = loongarch_cr_normal_name; loongarch_v_disname = loongarch_v_normal_name; @@ -87,6 +94,9 @@ set_default_loongarch_dis_options (void) static int parse_loongarch_dis_option (const char *option) { + if (strcmp (option, "no-aliases") == 0) + loongarch_dis_show_aliases = false; + if (strcmp (option, "numeric") == 0) { loongarch_r_disname = loongarch_r_normal_name; @@ -130,7 +140,7 @@ dis_one_arg (char esc1, char esc2, const char *bit_field, if (esc1) { if (need_comma) - info->fprintf_func (info->stream, ", "); + info->fprintf_func (info->stream, ", "); need_comma = 1; imm = loongarch_decode_imm (bit_field, insn, 1); u_imm = loongarch_decode_imm (bit_field, insn, 0); @@ -142,17 +152,24 @@ dis_one_arg (char esc1, char esc2, const char *bit_field, info->fprintf_func (info->stream, "%s", loongarch_r_disname[u_imm]); break; case 'f': + switch (esc2) + { + case 'c': + info->fprintf_func (info->stream, "%s", loongarch_fc_disname[u_imm]); + break; + default: info->fprintf_func (info->stream, "%s", loongarch_f_disname[u_imm]); + } break; case 'c': switch (esc2) - { - case 'r': - info->fprintf_func (info->stream, "%s", loongarch_cr_disname[u_imm]); - break; - default: - info->fprintf_func (info->stream, "%s", loongarch_c_disname[u_imm]); - } + { + case 'r': + info->fprintf_func (info->stream, "%s", loongarch_cr_disname[u_imm]); + break; + default: + info->fprintf_func (info->stream, "%s", loongarch_c_disname[u_imm]); + } break; case 'v': info->fprintf_func (info->stream, "%s", loongarch_v_disname[u_imm]); @@ -164,16 +181,13 @@ dis_one_arg (char esc1, char esc2, const char *bit_field, info->fprintf_func (info->stream, "0x%x", u_imm); break; case 's': - if (imm == 0) - info->fprintf_func (info->stream, "%d", imm); - else - info->fprintf_func (info->stream, "%d(0x%x)", imm, u_imm); + info->fprintf_func (info->stream, "%d", imm); switch (esc2) - { - case 'b': - info->insn_type = dis_branch; - info->target += imm; - } + { + case 'b': + info->insn_type = dis_branch; + info->target += imm; + } break; case '\0': need_comma = 0; @@ -185,7 +199,7 @@ static void disassemble_one (insn_t insn, struct disassemble_info *info) { const struct loongarch_opcode *opc = get_loongarch_opcode_by_binfmt (insn); - + #ifdef LOONGARCH_DEBUG char have_space[32] = { 0 }; insn_t t; @@ -194,25 +208,25 @@ disassemble_one (insn_t insn, struct disassemble_info *info) if (t_f) while (*t_f) { - while (('a' <= t_f[0] && t_f[0] <= 'z') - || ('A' <= t_f[0] && t_f[0] <= 'Z') - || t_f[0] == ',') - t_f++; - while (1) - { - i = strtol (t_f, &t_f, 10); - have_space[i] = 1; - t_f++; /* ':' */ - i += strtol (t_f, &t_f, 10); - have_space[i] = 1; - if (t_f[0] == '|') - t_f++; - else - break; - } - if (t_f[0] == '<') - t_f += 2; /* '<' '<' */ - strtol (t_f, &t_f, 10); + while (('a' <= t_f[0] && t_f[0] <= 'z') + || ('A' <= t_f[0] && t_f[0] <= 'Z') + || t_f[0] == ',') + t_f++; + while (1) + { + i = strtol (t_f, &t_f, 10); + have_space[i] = 1; + t_f++; /* ':' */ + i += strtol (t_f, &t_f, 10); + have_space[i] = 1; + if (t_f[0] == '|') + t_f++; + else + break; + } + if (t_f[0] == '<') + t_f += 2; /* '<' '<' */ + strtol (t_f, &t_f, 10); } have_space[28] = 1; @@ -221,19 +235,20 @@ disassemble_one (insn_t insn, struct disassemble_info *info) for (i = 31; 0 <= i; i--) { if (t & insn) - info->fprintf_func (info->stream, "1"); + info->fprintf_func (info->stream, "1"); else - info->fprintf_func (info->stream, "0"); + info->fprintf_func (info->stream, "0"); if (have_space[i]) - info->fprintf_func (info->stream, " "); + info->fprintf_func (info->stream, " "); t = t >> 1; } - info->fprintf_func (info->stream, "\t"); + info->fprintf_func (info->stream, "\t"); #endif if (!opc) { info->insn_type = dis_noninsn; + info->fprintf_func (info->stream, ".word\t\t"); info->fprintf_func (info->stream, "0x%08x", insn); return; } @@ -301,42 +316,9 @@ print_loongarch_disassembler_options (FILE *stream) The following LoongArch disassembler options are supported for use\n\ with the -M switch (multiple options should be separated by commas):\n")); + fprintf (stream, _("\n\ + no-aliases Use canonical instruction forms.\n")); fprintf (stream, _("\n\ numeric Print numeric register names, rather than ABI names.\n")); fprintf (stream, _("\n")); } - -int -loongarch_parse_dis_options (const char *opts_in) -{ - return parse_loongarch_dis_options (opts_in); -} - -static void -my_print_address_func (bfd_vma addr, struct disassemble_info *dinfo) -{ - dinfo->fprintf_func (dinfo->stream, "0x%llx", (long long) addr); -} - -void -loongarch_disassemble_one (int64_t pc, insn_t insn, - int (*fprintf_func) (void *stream, - const char *format, ...), - void *stream) -{ - static struct disassemble_info my_disinfo = - { - .print_address_func = my_print_address_func, - }; - static int not_init_yet = 1; - if (not_init_yet) - { - loongarch_parse_dis_options (NULL); - not_init_yet = 0; - } - - my_disinfo.fprintf_func = fprintf_func; - my_disinfo.stream = stream; - my_disinfo.target = pc; - disassemble_one (insn, &my_disinfo); -} diff --git a/opcodes/loongarch-opc.c b/opcodes/loongarch-opc.c index be0de61c..73a2271b 100644 --- a/opcodes/loongarch-opc.c +++ b/opcodes/loongarch-opc.c @@ -22,7 +22,10 @@ #include "opcode/loongarch.h" #include "libiberty.h" -struct loongarch_ASEs_option LARCH_opts; +struct loongarch_ASEs_option LARCH_opts = +{ + .relax = 1 +}; size_t loongarch_insn_length (insn_t insn ATTRIBUTE_UNUSED) @@ -42,14 +45,14 @@ const char *const loongarch_r_lp64_name[32] = { "$zero", "$ra", "$tp", "$sp", "$a0", "$a1", "$a2", "$a3", "$a4", "$a5", "$a6", "$a7", "$t0", "$t1", "$t2", "$t3", - "$t4", "$t5", "$t6", "$t7", "$t8", "$x", "$fp", "$s0", + "$t4", "$t5", "$t6", "$t7", "$t8", "$r21","$fp", "$s0", "$s1", "$s2", "$s3", "$s4", "$s5", "$s6", "$s7", "$s8", }; -const char *const loongarch_r_lp64_name1[32] = +const char *const loongarch_r_lp64_name_deprecated[32] = { "", "", "", "", "$v0", "$v1", "", "", "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", + "", "", "", "", "", "$x", "", "", "", "", "", "", "", "", "", "", }; const char *const loongarch_f_normal_name[32] = @@ -68,12 +71,22 @@ const char *const loongarch_f_lp64_name[32] = "$fs0", "$fs1", "$fs2", "$fs3", "$fs4", "$fs5", "$fs6", "$fs7", }; -const char *const loongarch_f_lp64_name1[32] = +const char *const loongarch_f_lp64_name_deprecated[32] = { "$fv0", "$fv1", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", }; +const char *const loongarch_fc_normal_name[4] = +{ + "$fcsr0", "$fcsr1", "$fcsr2", "$fcsr3", +}; + +const char *const loongarch_fc_numeric_name[4] = +{ + "$r0", "$r1", "$r2", "$r3", +}; + const char *const loongarch_c_normal_name[8] = { "$fcc0", "$fcc1", "$fcc2", "$fcc3", "$fcc4", "$fcc5", "$fcc6", "$fcc7", @@ -142,10 +155,10 @@ const char *const loongarch_x_normal_name[32] = &LARCH_opts.ase_lp64 /* got32 abs. */ #define INSN_LA_GOT32_ABS \ - "lu12i.w %1,%%got_hi20(%2);" \ + "lu12i.w %1,%%got_hi20(%2);" \ "ori %1,%1,%%got_lo12(%2);" \ - "ld.w %1,%1,0;", \ - &LARCH_opts.ase_gabs, \ + "ld.w %1,%1,0;", \ + &LARCH_opts.ase_gabs, \ &LARCH_opts.ase_lp64 #define INSN_LA_GOT64 \ "pcalau12i %1,%%got_pc_hi20(%2);" \ @@ -153,7 +166,7 @@ const char *const loongarch_x_normal_name[32] = &LARCH_opts.ase_lp64, 0 /* got64 abs. */ #define INSN_LA_GOT64_LARGE_ABS \ - "lu12i.w %1,%%got_hi20(%2);" \ + "lu12i.w %1,%%got_hi20(%2);" \ "ori %1,%1,%%got_lo12(%2);" \ "lu32i.d %1,%%got64_lo20(%2);" \ "lu52i.d %1,%1,%%got64_hi12(%2);" \ @@ -186,11 +199,11 @@ const char *const loongarch_x_normal_name[32] = #define INSN_LA_TLS_IE32 \ "pcalau12i %1,%%ie_pc_hi20(%2);" \ - "ld.w %1,%1,%%ie_pc_lo12(%2);", \ + "ld.w %1,%1,%%ie_pc_lo12(%2);", \ &LARCH_opts.ase_ilp32, \ &LARCH_opts.ase_lp64 /* For ie32 abs. */ -#define INSN_LA_TLS_IE32_ABS \ +#define INSN_LA_TLS_IE32_ABS \ "lu12i.w %1,%%ie_hi20(%2);" \ "ori %1,%1,%%ie_lo12(%2);" \ "ld.w %1,%1,0", \ @@ -198,14 +211,14 @@ const char *const loongarch_x_normal_name[32] = &LARCH_opts.ase_lp64 #define INSN_LA_TLS_IE64 \ "pcalau12i %1,%%ie_pc_hi20(%2);" \ - "ld.d %1,%1,%%ie_pc_lo12(%2);", \ + "ld.d %1,%1,%%ie_pc_lo12(%2);", \ &LARCH_opts.ase_lp64, 0 /* For ie64 pic. */ #define INSN_LA_TLS_IE64_LARGE_PCREL \ "pcalau12i %1,%%ie_pc_hi20(%3);" \ - "addi.d %2,$r0,%%ie_pc_lo12(%3);" \ - "lu32i.d %2,%%ie64_pc_lo20(%3);" \ - "lu52i.d %2,%2,%%ie64_pc_hi12(%3);"\ + "addi.d %2,$r0,%%ie_pc_lo12(%3);" \ + "lu32i.d %2,%%ie64_pc_lo20(%3);" \ + "lu52i.d %2,%2,%%ie64_pc_hi12(%3);" \ "ldx.d %1,%1,%2;", \ &LARCH_opts.ase_lp64, \ &LARCH_opts.ase_gabs @@ -213,8 +226,8 @@ const char *const loongarch_x_normal_name[32] = #define INSN_LA_TLS_IE64_LARGE_ABS \ "lu12i.w %1,%%ie_hi20(%2);" \ "ori %1,%1,%%ie_lo12(%2);" \ - "lu32i.d %1,%%ie64_lo20(%2);" \ - "lu52i.d %1,%1,%%ie64_hi12(%2);" \ + "lu32i.d %1,%%ie64_lo20(%2);" \ + "lu52i.d %1,%1,%%ie64_hi12(%2);" \ "ld.d %1,%1,0", \ &LARCH_opts.ase_lp64, \ &LARCH_opts.ase_gpcr @@ -328,12 +341,32 @@ static struct loongarch_opcode loongarch_macro_opcodes[] = { 0, 0, "la.tls.gd", "r,l", INSN_LA_TLS_GD64_LARGE_ABS, 0 }, { 0, 0, "la.tls.gd", "r,r,l", INSN_LA_TLS_GD64_LARGE_PCREL, 0 }, - { 0 } /* Terminate the list. */ + { 0, 0, 0, 0, 0, 0, 0, 0 } /* Terminate the list. */ +}; + + +static struct loongarch_opcode loongarch_alias_opcodes[] = +{ + /* match, mask, name, format, macro, include, exclude, pinfo. */ + { 0x00150000, 0xfffffc00, "move", "r0:5,r5:5", 0, 0, 0, INSN_DIS_ALIAS }, /* or rd, rj, zero */ + { 0x02800000, 0xffc003e0, "li.w", "r0:5,s10:12", 0, 0, 0, INSN_DIS_ALIAS }, /* addi.w rd, zero, simm */ + { 0x02c00000, 0xffc003e0, "li.d", "r0:5,s10:12", 0, 0, 0, INSN_DIS_ALIAS }, /* addi.d rd, zero, simm */ + { 0x03400000, 0xffffffff, "nop", "", 0, 0, 0, INSN_DIS_ALIAS }, /* andi zero, zero, 0 */ + { 0x03800000, 0xffc003e0, "li.w", "r0:5,u10:12", 0, 0, 0, INSN_DIS_ALIAS }, /* ori rd, zero, uimm */ + /* ret must come before jr because it is more specific. */ + { 0x4c000020, 0xffffffff, "ret", "", 0, 0, 0, INSN_DIS_ALIAS }, /* jirl zero, ra, 0 */ + { 0x4c000000, 0xfffffc1f, "jr", "r5:5", 0, 0, 0, INSN_DIS_ALIAS }, /* jirl zero, rj, 0 */ + { 0x60000000, 0xfc00001f, "bltz", "r5:5,sb10:16<<2", 0, 0, 0, INSN_DIS_ALIAS }, /* blt rj, zero, offset */ + { 0x60000000, 0xfc0003e0, "bgtz", "r0:5,sb10:16<<2", 0, 0, 0, INSN_DIS_ALIAS }, /* blt zero, rd, offset */ + { 0x64000000, 0xfc00001f, "bgez", "r5:5,sb10:16<<2", 0, 0, 0, INSN_DIS_ALIAS }, /* bge rj, zero, offset */ + { 0x64000000, 0xfc0003e0, "blez", "r0:5,sb10:16<<2", 0, 0, 0, INSN_DIS_ALIAS }, /* bge zero, rd, offset */ + { 0, 0, 0, 0, 0, 0, 0, 0 } /* Terminate the list. */ }; static struct loongarch_opcode loongarch_fix_opcodes[] = { /* match, mask, name, format, macro, include, exclude, pinfo. */ + { 0x0, 0x0, "move", "r,r", "or %1,%2,$r0", 0, 0, 0 }, { 0x00001000, 0xfffffc00, "clo.w", "r0:5,r5:5", 0, 0, 0, 0 }, { 0x00001400, 0xfffffc00, "clz.w", "r0:5,r5:5", 0, 0, 0, 0 }, { 0x00001800, 0xfffffc00, "cto.w", "r0:5,r5:5", 0, 0, 0, 0 }, @@ -354,9 +387,7 @@ static struct loongarch_opcode loongarch_fix_opcodes[] = { 0x00005400, 0xfffffc00, "bitrev.d", "r0:5,r5:5", 0, 0, 0, 0 }, { 0x00005800, 0xfffffc00, "ext.w.h", "r0:5,r5:5", 0, 0, 0, 0 }, { 0x00005c00, 0xfffffc00, "ext.w.b", "r0:5,r5:5", 0, 0, 0, 0 }, - /* or %1,%2,$r0 */ - { 0x00150000, 0xfffffc00, "move", "r0:5,r5:5", 0, 0, 0, 0 }, - { 0x00006000, 0xfffffc00, "rdtimel.w", "r0:5,r5:5", 0, 0, 0, 0 }, + { 0x00006000, 0xfffffc00, "rdtimel.w", "r0:5,r5:5", 0, 0, 0, 0 }, { 0x00006400, 0xfffffc00, "rdtimeh.w", "r0:5,r5:5", 0, 0, 0, 0 }, { 0x00006800, 0xfffffc00, "rdtime.d", "r0:5,r5:5", 0, 0, 0, 0 }, { 0x00006c00, 0xfffffc00, "cpucfg", "r0:5,r5:5", 0, 0, 0, 0 }, @@ -428,7 +459,7 @@ static struct loongarch_opcode loongarch_fix_opcodes[] = { 0x00608000, 0xffe08000, "bstrpick.w", "r0:5,r5:5,u16:5,u10:5", 0, 0, 0, 0 }, { 0x00800000, 0xffc00000, "bstrins.d", "r0:5,r5:5,u16:6,u10:6", 0, 0, 0, 0 }, { 0x00c00000, 0xffc00000, "bstrpick.d", "r0:5,r5:5,u16:6,u10:6", 0, 0, 0, 0 }, - { 0 } /* Terminate the list. */ + { 0, 0, 0, 0, 0, 0, 0, 0 } /* Terminate the list. */ }; static struct loongarch_opcode loongarch_single_float_opcodes[] = @@ -456,8 +487,8 @@ static struct loongarch_opcode loongarch_single_float_opcodes[] = { 0x0114ac00, 0xfffffc00, "movgr2frh.w", "f0:5,r5:5", 0, 0, 0, 0 }, { 0x0114b400, 0xfffffc00, "movfr2gr.s", "r0:5,f5:5", 0, 0, 0, 0 }, { 0x0114bc00, 0xfffffc00, "movfrh2gr.s", "r0:5,f5:5", 0, 0, 0, 0 }, - { 0x0114c000, 0xfffffc00, "movgr2fcsr", "r0:5,r5:5", 0, 0, 0, 0 }, - { 0x0114c800, 0xfffffc00, "movfcsr2gr", "r0:5,r5:5", 0, 0, 0, 0 }, + { 0x0114c000, 0xfffffc1c, "movgr2fcsr", "fc0:2,r5:5", 0, 0, 0, 0 }, + { 0x0114c800, 0xffffff80, "movfcsr2gr", "r0:5,fc5:2", 0, 0, 0, 0 }, { 0x0114d000, 0xfffffc18, "movfr2cf", "c0:3,f5:5", 0, 0, 0, 0 }, { 0x0114d400, 0xffffff00, "movcf2fr", "f0:5,c5:3", 0, 0, 0, 0 }, { 0x0114d800, 0xfffffc18, "movgr2cf", "c0:3,r5:5", 0, 0, 0, 0 }, @@ -475,7 +506,7 @@ static struct loongarch_opcode loongarch_single_float_opcodes[] = { 0x011d1000, 0xfffffc00, "ffint.s.w", "f0:5,f5:5", 0, 0, 0, 0 }, { 0x011d1800, 0xfffffc00, "ffint.s.l", "f0:5,f5:5", 0, 0, 0, 0 }, { 0x011e4400, 0xfffffc00, "frint.s", "f0:5,f5:5", 0, 0, 0, 0 }, - { 0 } /* Terminate the list. */ + { 0, 0, 0, 0, 0, 0, 0, 0 } /* Terminate the list. */ }; static struct loongarch_opcode loongarch_double_float_opcodes[] = { @@ -515,7 +546,7 @@ static struct loongarch_opcode loongarch_double_float_opcodes[] = { 0x011d2000, 0xfffffc00, "ffint.d.w", "f0:5,f5:5", 0, 0, 0, 0 }, { 0x011d2800, 0xfffffc00, "ffint.d.l", "f0:5,f5:5", 0, 0, 0, 0 }, { 0x011e4800, 0xfffffc00, "frint.d", "f0:5,f5:5", 0, 0, 0, 0 }, - { 0 } /* Terminate the list. */ + { 0, 0, 0, 0, 0, 0, 0, 0 } /* Terminate the list. */ }; static struct loongarch_opcode loongarch_imm_opcodes[] = @@ -537,7 +568,7 @@ static struct loongarch_opcode loongarch_imm_opcodes[] = { 0x1a000000, 0xfe000000, "pcalau12i", "r0:5,s5:20", 0, 0, 0, 0 }, { 0x1c000000, 0xfe000000, "pcaddu12i", "r0:5,s5:20", 0, 0, 0, 0 }, { 0x1e000000, 0xfe000000, "pcaddu18i", "r0:5,s5:20", 0, 0, 0, 0 }, - { 0 } /* Terminate the list. */ + { 0, 0, 0, 0, 0, 0, 0, 0 } /* Terminate the list. */ }; static struct loongarch_opcode loongarch_privilege_opcodes[] = @@ -566,44 +597,100 @@ static struct loongarch_opcode loongarch_privilege_opcodes[] = { 0x06483800, 0xffffffff, "ertn", "", 0, 0, 0, 0 }, { 0x06488000, 0xffff8000, "idle", "u0:15", 0, 0, 0, 0 }, { 0x06498000, 0xffff8000, "invtlb", "u0:5,r5:5,r10:5", 0, 0, 0, 0 }, - { 0 } /* Terminate the list. */ + { 0, 0, 0, 0, 0, 0, 0, 0 } /* Terminate the list. */ }; static struct loongarch_opcode loongarch_4opt_single_float_opcodes[] = { - /* match, mask, name, format, macro, include, exclude, pinfo. */ - { 0x08100000, 0xfff00000, "fmadd.s", "f0:5,f5:5,f10:5,f15:5", 0, 0, 0, 0 }, - { 0x08500000, 0xfff00000, "fmsub.s", "f0:5,f5:5,f10:5,f15:5", 0, 0, 0, 0 }, - { 0x08900000, 0xfff00000, "fnmadd.s", "f0:5,f5:5,f10:5,f15:5", 0, 0, 0, 0 }, - { 0x08d00000, 0xfff00000, "fnmsub.s", "f0:5,f5:5,f10:5,f15:5", 0, 0, 0, 0 }, - { 0x0c100000, 0xffff8018, "fcmp.caf.s", "c0:3,f5:5,f10:5", 0, 0, 0, 0 }, - { 0x0c108000, 0xffff8018, "fcmp.saf.s", "c0:3,f5:5,f10:5", 0, 0, 0, 0 }, - { 0x0c110000, 0xffff8018, "fcmp.clt.s", "c0:3,f5:5,f10:5", 0, 0, 0, 0 }, - { 0x0c118000, 0xffff8018, "fcmp.slt.s", "c0:3,f5:5,f10:5", 0, 0, 0, 0 }, - { 0x0c118000, 0xffff8018, "fcmp.sgt.s", "c0:3,f10:5,f5:5", 0, 0, 0, 0 }, - { 0x0c120000, 0xffff8018, "fcmp.ceq.s", "c0:3,f5:5,f10:5", 0, 0, 0, 0 }, - { 0x0c128000, 0xffff8018, "fcmp.seq.s", "c0:3,f5:5,f10:5", 0, 0, 0, 0 }, - { 0x0c130000, 0xffff8018, "fcmp.cle.s", "c0:3,f5:5,f10:5", 0, 0, 0, 0 }, - { 0x0c138000, 0xffff8018, "fcmp.sle.s", "c0:3,f5:5,f10:5", 0, 0, 0, 0 }, - { 0x0c138000, 0xffff8018, "fcmp.sge.s", "c0:3,f10:5,f5:5", 0, 0, 0, 0 }, - { 0x0c140000, 0xffff8018, "fcmp.cun.s", "c0:3,f5:5,f10:5", 0, 0, 0, 0 }, - { 0x0c148000, 0xffff8018, "fcmp.sun.s", "c0:3,f5:5,f10:5", 0, 0, 0, 0 }, - { 0x0c150000, 0xffff8018, "fcmp.cult.s", "c0:3,f5:5,f10:5", 0, 0, 0, 0 }, - { 0x0c150000, 0xffff8018, "fcmp.cugt.s", "c0:3,f10:5,f5:5", 0, 0, 0, 0 }, - { 0x0c158000, 0xffff8018, "fcmp.sult.s", "c0:3,f5:5,f10:5", 0, 0, 0, 0 }, - { 0x0c160000, 0xffff8018, "fcmp.cueq.s", "c0:3,f5:5,f10:5", 0, 0, 0, 0 }, - { 0x0c168000, 0xffff8018, "fcmp.sueq.s", "c0:3,f5:5,f10:5", 0, 0, 0, 0 }, - { 0x0c170000, 0xffff8018, "fcmp.cule.s", "c0:3,f5:5,f10:5", 0, 0, 0, 0 }, - { 0x0c170000, 0xffff8018, "fcmp.cuge.s", "c0:3,f10:5,f5:5", 0, 0, 0, 0 }, - { 0x0c178000, 0xffff8018, "fcmp.sule.s", "c0:3,f5:5,f10:5", 0, 0, 0, 0 }, - { 0x0c180000, 0xffff8018, "fcmp.cne.s", "c0:3,f5:5,f10:5", 0, 0, 0, 0 }, - { 0x0c188000, 0xffff8018, "fcmp.sne.s", "c0:3,f5:5,f10:5", 0, 0, 0, 0 }, - { 0x0c1a0000, 0xffff8018, "fcmp.cor.s", "c0:3,f5:5,f10:5", 0, 0, 0, 0 }, - { 0x0c1a8000, 0xffff8018, "fcmp.sor.s", "c0:3,f5:5,f10:5", 0, 0, 0, 0 }, - { 0x0c1c0000, 0xffff8018, "fcmp.cune.s", "c0:3,f5:5,f10:5", 0, 0, 0, 0 }, - { 0x0c1c8000, 0xffff8018, "fcmp.sune.s", "c0:3,f5:5,f10:5", 0, 0, 0, 0 }, - { 0x0d000000, 0xfffc0000, "fsel", "f0:5,f5:5,f10:5,c15:3", 0, 0, 0, 0 }, - { 0 } /* Terminate the list. */ + /* match, mask, name, format, macro, include, exclude, pinfo. */ + { 0x08100000, 0xfff00000, "fmadd.s", "f0:5,f5:5,f10:5,f15:5", 0, 0, 0, 0 }, + { 0x08500000, 0xfff00000, "fmsub.s", "f0:5,f5:5,f10:5,f15:5", 0, 0, 0, 0 }, + { 0x08900000, 0xfff00000, "fnmadd.s", "f0:5,f5:5,f10:5,f15:5", 0, 0, 0, 0 }, + { 0x08d00000, 0xfff00000, "fnmsub.s", "f0:5,f5:5,f10:5,f15:5", 0, 0, 0, 0 }, + { 0x09100000, 0xfff00000, "vfmadd.s", "v0:5,v5:5,v10:5,v15:5", 0, 0, 0, 0 }, + { 0x09500000, 0xfff00000, "vfmsub.s", "v0:5,v5:5,v10:5,v15:5", 0, 0, 0, 0 }, + { 0x09900000, 0xfff00000, "vfnmadd.s", "v0:5,v5:5,v10:5,v15:5", 0, 0, 0, 0 }, + { 0x09d00000, 0xfff00000, "vfnmsub.s", "v0:5,v5:5,v10:5,v15:5", 0, 0, 0, 0 }, + { 0x0a100000, 0xfff00000, "xvfmadd.s", "x0:5,x5:5,x10:5,x15:5", 0, 0, 0, 0 }, + { 0x0a500000, 0xfff00000, "xvfmsub.s", "x0:5,x5:5,x10:5,x15:5", 0, 0, 0, 0 }, + { 0x0a900000, 0xfff00000, "xvfnmadd.s", "x0:5,x5:5,x10:5,x15:5", 0, 0, 0, 0 }, + { 0x0ad00000, 0xfff00000, "xvfnmsub.s", "x0:5,x5:5,x10:5,x15:5", 0, 0, 0, 0 }, + { 0x0c100000, 0xffff8018, "fcmp.caf.s", "c0:3,f5:5,f10:5", 0, 0, 0, 0 }, + { 0x0c108000, 0xffff8018, "fcmp.saf.s", "c0:3,f5:5,f10:5", 0, 0, 0, 0 }, + { 0x0c110000, 0xffff8018, "fcmp.clt.s", "c0:3,f5:5,f10:5", 0, 0, 0, 0 }, + { 0x0c118000, 0xffff8018, "fcmp.slt.s", "c0:3,f5:5,f10:5", 0, 0, 0, 0 }, + { 0x0c118000, 0xffff8018, "fcmp.sgt.s", "c0:3,f10:5,f5:5", 0, 0, 0, 0 }, + { 0x0c120000, 0xffff8018, "fcmp.ceq.s", "c0:3,f5:5,f10:5", 0, 0, 0, 0 }, + { 0x0c128000, 0xffff8018, "fcmp.seq.s", "c0:3,f5:5,f10:5", 0, 0, 0, 0 }, + { 0x0c130000, 0xffff8018, "fcmp.cle.s", "c0:3,f5:5,f10:5", 0, 0, 0, 0 }, + { 0x0c138000, 0xffff8018, "fcmp.sle.s", "c0:3,f5:5,f10:5", 0, 0, 0, 0 }, + { 0x0c138000, 0xffff8018, "fcmp.sge.s", "c0:3,f10:5,f5:5", 0, 0, 0, 0 }, + { 0x0c140000, 0xffff8018, "fcmp.cun.s", "c0:3,f5:5,f10:5", 0, 0, 0, 0 }, + { 0x0c148000, 0xffff8018, "fcmp.sun.s", "c0:3,f5:5,f10:5", 0, 0, 0, 0 }, + { 0x0c150000, 0xffff8018, "fcmp.cult.s", "c0:3,f5:5,f10:5", 0, 0, 0, 0 }, + { 0x0c150000, 0xffff8018, "fcmp.cugt.s", "c0:3,f10:5,f5:5", 0, 0, 0, 0 }, + { 0x0c158000, 0xffff8018, "fcmp.sult.s", "c0:3,f5:5,f10:5", 0, 0, 0, 0 }, + { 0x0c160000, 0xffff8018, "fcmp.cueq.s", "c0:3,f5:5,f10:5", 0, 0, 0, 0 }, + { 0x0c168000, 0xffff8018, "fcmp.sueq.s", "c0:3,f5:5,f10:5", 0, 0, 0, 0 }, + { 0x0c170000, 0xffff8018, "fcmp.cule.s", "c0:3,f5:5,f10:5", 0, 0, 0, 0 }, + { 0x0c170000, 0xffff8018, "fcmp.cuge.s", "c0:3,f10:5,f5:5", 0, 0, 0, 0 }, + { 0x0c178000, 0xffff8018, "fcmp.sule.s", "c0:3,f5:5,f10:5", 0, 0, 0, 0 }, + { 0x0c180000, 0xffff8018, "fcmp.cne.s", "c0:3,f5:5,f10:5", 0, 0, 0, 0 }, + { 0x0c188000, 0xffff8018, "fcmp.sne.s", "c0:3,f5:5,f10:5", 0, 0, 0, 0 }, + { 0x0c1a0000, 0xffff8018, "fcmp.cor.s", "c0:3,f5:5,f10:5", 0, 0, 0, 0 }, + { 0x0c1a8000, 0xffff8018, "fcmp.sor.s", "c0:3,f5:5,f10:5", 0, 0, 0, 0 }, + { 0x0c1c0000, 0xffff8018, "fcmp.cune.s", "c0:3,f5:5,f10:5", 0, 0, 0, 0 }, + { 0x0c1c8000, 0xffff8018, "fcmp.sune.s", "c0:3,f5:5,f10:5", 0, 0, 0, 0 }, + { 0x0c500000, 0xffff8000, "vfcmp.caf.s", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x0c508000, 0xffff8000, "vfcmp.saf.s", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x0c510000, 0xffff8000, "vfcmp.clt.s", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x0c518000, 0xffff8000, "vfcmp.slt.s", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x0c520000, 0xffff8000, "vfcmp.ceq.s", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x0c528000, 0xffff8000, "vfcmp.seq.s", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x0c530000, 0xffff8000, "vfcmp.cle.s", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x0c538000, 0xffff8000, "vfcmp.sle.s", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x0c540000, 0xffff8000, "vfcmp.cun.s", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x0c548000, 0xffff8000, "vfcmp.sun.s", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x0c550000, 0xffff8000, "vfcmp.cult.s", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x0c558000, 0xffff8000, "vfcmp.sult.s", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x0c560000, 0xffff8000, "vfcmp.cueq.s", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x0c568000, 0xffff8000, "vfcmp.sueq.s", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x0c570000, 0xffff8000, "vfcmp.cule.s", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x0c578000, 0xffff8000, "vfcmp.sule.s", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x0c580000, 0xffff8000, "vfcmp.cne.s", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x0c588000, 0xffff8000, "vfcmp.sne.s", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x0c5a0000, 0xffff8000, "vfcmp.cor.s", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x0c5a8000, 0xffff8000, "vfcmp.sor.s", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x0c5c0000, 0xffff8000, "vfcmp.cune.s", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x0c5c8000, 0xffff8000, "vfcmp.sune.s", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x0c900000, 0xffff8000, "xvfcmp.caf.s", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x0c908000, 0xffff8000, "xvfcmp.saf.s", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x0c910000, 0xffff8000, "xvfcmp.clt.s", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x0c918000, 0xffff8000, "xvfcmp.slt.s", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x0c920000, 0xffff8000, "xvfcmp.ceq.s", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x0c928000, 0xffff8000, "xvfcmp.seq.s", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x0c930000, 0xffff8000, "xvfcmp.cle.s", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x0c938000, 0xffff8000, "xvfcmp.sle.s", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x0c940000, 0xffff8000, "xvfcmp.cun.s", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x0c948000, 0xffff8000, "xvfcmp.sun.s", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x0c950000, 0xffff8000, "xvfcmp.cult.s", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x0c958000, 0xffff8000, "xvfcmp.sult.s", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x0c960000, 0xffff8000, "xvfcmp.cueq.s", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x0c968000, 0xffff8000, "xvfcmp.sueq.s", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x0c970000, 0xffff8000, "xvfcmp.cule.s", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x0c978000, 0xffff8000, "xvfcmp.sule.s", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x0c980000, 0xffff8000, "xvfcmp.cne.s", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x0c988000, 0xffff8000, "xvfcmp.sne.s", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x0c9a0000, 0xffff8000, "xvfcmp.cor.s", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x0c9a8000, 0xffff8000, "xvfcmp.sor.s", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x0c9c0000, 0xffff8000, "xvfcmp.cune.s", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x0c9c8000, 0xffff8000, "xvfcmp.sune.s", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x0d000000, 0xfffc0000, "fsel", "f0:5,f5:5,f10:5,c15:3", 0, 0, 0, 0 }, + { 0x0d100000, 0xfff00000, "vbitsel.v", "v0:5,v5:5,v10:5,v15:5", 0, 0, 0, 0 }, + { 0x0d200000, 0xfff00000, "xvbitsel.v", "x0:5,x5:5,x10:5,x15:5", 0, 0, 0, 0 }, + { 0x0d500000, 0xfff00000, "vshuf.b", "v0:5,v5:5,v10:5,v15:5", 0, 0, 0, 0 }, + { 0x0d600000, 0xfff00000, "xvshuf.b", "x0:5,x5:5,x10:5,x15:5", 0, 0, 0, 0 }, + { 0, 0, 0, 0, 0, 0, 0, 0 } /* Terminate the list. */ }; static struct loongarch_opcode loongarch_4opt_double_float_opcodes[] = @@ -613,6 +700,14 @@ static struct loongarch_opcode loongarch_4opt_double_float_opcodes[] = { 0x08600000, 0xfff00000, "fmsub.d", "f0:5,f5:5,f10:5,f15:5", 0, 0, 0, 0 }, { 0x08a00000, 0xfff00000, "fnmadd.d", "f0:5,f5:5,f10:5,f15:5", 0, 0, 0, 0 }, { 0x08e00000, 0xfff00000, "fnmsub.d", "f0:5,f5:5,f10:5,f15:5", 0, 0, 0, 0 }, + { 0x09200000, 0xfff00000, "vfmadd.d", "v0:5,v5:5,v10:5,v15:5", 0, 0, 0, 0}, + { 0x09600000, 0xfff00000, "vfmsub.d", "v0:5,v5:5,v10:5,v15:5", 0, 0, 0, 0}, + { 0x09a00000, 0xfff00000, "vfnmadd.d", "v0:5,v5:5,v10:5,v15:5", 0, 0, 0, 0}, + { 0x09e00000, 0xfff00000, "vfnmsub.d", "v0:5,v5:5,v10:5,v15:5", 0, 0, 0, 0}, + { 0x0a200000, 0xfff00000, "xvfmadd.d", "x0:5,x5:5,x10:5,x15:5", 0, 0, 0, 0}, + { 0x0a600000, 0xfff00000, "xvfmsub.d", "x0:5,x5:5,x10:5,x15:5", 0, 0, 0, 0}, + { 0x0aa00000, 0xfff00000, "xvfnmadd.d", "x0:5,x5:5,x10:5,x15:5", 0, 0, 0, 0}, + { 0x0ae00000, 0xfff00000, "xvfnmsub.d", "x0:5,x5:5,x10:5,x15:5", 0, 0, 0, 0}, { 0x0c200000, 0xffff8018, "fcmp.caf.d", "c0:3,f5:5,f10:5", 0, 0, 0, 0 }, { 0x0c208000, 0xffff8018, "fcmp.saf.d", "c0:3,f5:5,f10:5", 0, 0, 0, 0 }, { 0x0c210000, 0xffff8018, "fcmp.clt.d", "c0:3,f5:5,f10:5", 0, 0, 0, 0 }, @@ -639,32 +734,76 @@ static struct loongarch_opcode loongarch_4opt_double_float_opcodes[] = { 0x0c2a8000, 0xffff8018, "fcmp.sor.d", "c0:3,f5:5,f10:5", 0, 0, 0, 0 }, { 0x0c2c0000, 0xffff8018, "fcmp.cune.d", "c0:3,f5:5,f10:5", 0, 0, 0, 0 }, { 0x0c2c8000, 0xffff8018, "fcmp.sune.d", "c0:3,f5:5,f10:5", 0, 0, 0, 0 }, - { 0 } /* Terminate the list. */ + { 0x0c600000, 0xffff8000, "vfcmp.caf.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x0c608000, 0xffff8000, "vfcmp.saf.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x0c610000, 0xffff8000, "vfcmp.clt.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x0c618000, 0xffff8000, "vfcmp.slt.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x0c620000, 0xffff8000, "vfcmp.ceq.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x0c628000, 0xffff8000, "vfcmp.seq.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x0c630000, 0xffff8000, "vfcmp.cle.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x0c638000, 0xffff8000, "vfcmp.sle.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x0c640000, 0xffff8000, "vfcmp.cun.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x0c648000, 0xffff8000, "vfcmp.sun.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x0c650000, 0xffff8000, "vfcmp.cult.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x0c658000, 0xffff8000, "vfcmp.sult.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x0c660000, 0xffff8000, "vfcmp.cueq.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x0c668000, 0xffff8000, "vfcmp.sueq.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x0c670000, 0xffff8000, "vfcmp.cule.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x0c678000, 0xffff8000, "vfcmp.sule.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x0c680000, 0xffff8000, "vfcmp.cne.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x0c688000, 0xffff8000, "vfcmp.sne.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x0c6a0000, 0xffff8000, "vfcmp.cor.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x0c6a8000, 0xffff8000, "vfcmp.sor.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x0c6c0000, 0xffff8000, "vfcmp.cune.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x0c6c8000, 0xffff8000, "vfcmp.sune.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x0ca00000, 0xffff8000, "xvfcmp.caf.d", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x0ca08000, 0xffff8000, "xvfcmp.saf.d", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x0ca10000, 0xffff8000, "xvfcmp.clt.d", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x0ca18000, 0xffff8000, "xvfcmp.slt.d", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x0ca20000, 0xffff8000, "xvfcmp.ceq.d", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x0ca28000, 0xffff8000, "xvfcmp.seq.d", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x0ca30000, 0xffff8000, "xvfcmp.cle.d", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x0ca38000, 0xffff8000, "xvfcmp.sle.d", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x0ca40000, 0xffff8000, "xvfcmp.cun.d", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x0ca48000, 0xffff8000, "xvfcmp.sun.d", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x0ca50000, 0xffff8000, "xvfcmp.cult.d", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x0ca58000, 0xffff8000, "xvfcmp.sult.d", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x0ca60000, 0xffff8000, "xvfcmp.cueq.d", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x0ca68000, 0xffff8000, "xvfcmp.sueq.d", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x0ca70000, 0xffff8000, "xvfcmp.cule.d", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x0ca78000, 0xffff8000, "xvfcmp.sule.d", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x0ca80000, 0xffff8000, "xvfcmp.cne.d", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x0ca88000, 0xffff8000, "xvfcmp.sne.d", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x0caa0000, 0xffff8000, "xvfcmp.cor.d", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x0caa8000, 0xffff8000, "xvfcmp.sor.d", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x0cac0000, 0xffff8000, "xvfcmp.cune.d", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x0cac8000, 0xffff8000, "xvfcmp.sune.d", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0, 0, 0, 0, 0, 0, 0, 0 } /* Terminate the list. */ }; static struct loongarch_opcode loongarch_load_store_opcodes[] = { /* match, mask, name, format, macro, include, exclude, pinfo. */ - { 0x20000000, 0xff000000, "ll.w", "r0:5,r5:5,s10:14<<2", 0, 0, 0, 0 }, - { 0x21000000, 0xff000000, "sc.w", "r0:5,r5:5,s10:14<<2", 0, 0, 0, 0 }, - { 0x22000000, 0xff000000, "ll.d", "r0:5,r5:5,s10:14<<2", 0, 0, 0, 0 }, - { 0x23000000, 0xff000000, "sc.d", "r0:5,r5:5,s10:14<<2", 0, 0, 0, 0 }, - { 0x24000000, 0xff000000, "ldptr.w", "r0:5,r5:5,s10:14<<2", 0, 0, 0, 0 }, - { 0x25000000, 0xff000000, "stptr.w", "r0:5,r5:5,s10:14<<2", 0, 0, 0, 0 }, - { 0x26000000, 0xff000000, "ldptr.d", "r0:5,r5:5,s10:14<<2", 0, 0, 0, 0 }, - { 0x27000000, 0xff000000, "stptr.d", "r0:5,r5:5,s10:14<<2", 0, 0, 0, 0 }, - { 0x28000000, 0xffc00000, "ld.b", "r0:5,r5:5,s10:12", 0, 0, 0, 0 }, - { 0x28400000, 0xffc00000, "ld.h", "r0:5,r5:5,s10:12", 0, 0, 0, 0 }, - { 0x28800000, 0xffc00000, "ld.w", "r0:5,r5:5,s10:12", 0, 0, 0, 0 }, - { 0x28c00000, 0xffc00000, "ld.d", "r0:5,r5:5,s10:12", 0, 0, 0, 0 }, - { 0x29000000, 0xffc00000, "st.b", "r0:5,r5:5,s10:12", 0, 0, 0, 0 }, - { 0x29400000, 0xffc00000, "st.h", "r0:5,r5:5,s10:12", 0, 0, 0, 0 }, - { 0x29800000, 0xffc00000, "st.w", "r0:5,r5:5,s10:12", 0, 0, 0, 0 }, - { 0x29c00000, 0xffc00000, "st.d", "r0:5,r5:5,s10:12", 0, 0, 0, 0 }, - { 0x2a000000, 0xffc00000, "ld.bu", "r0:5,r5:5,s10:12", 0, 0, 0, 0 }, - { 0x2a400000, 0xffc00000, "ld.hu", "r0:5,r5:5,s10:12", 0, 0, 0, 0 }, - { 0x2a800000, 0xffc00000, "ld.wu", "r0:5,r5:5,s10:12", 0, 0, 0, 0 }, - { 0x2ac00000, 0xffc00000, "preld", "u0:5,r5:5,s10:12", 0, 0, 0, 0 }, + { 0x20000000, 0xff000000, "ll.w", "r0:5,r5:5,so10:14<<2", 0, 0, 0, 0 }, + { 0x21000000, 0xff000000, "sc.w", "r0:5,r5:5,so10:14<<2", 0, 0, 0, 0 }, + { 0x22000000, 0xff000000, "ll.d", "r0:5,r5:5,so10:14<<2", 0, 0, 0, 0 }, + { 0x23000000, 0xff000000, "sc.d", "r0:5,r5:5,so10:14<<2", 0, 0, 0, 0 }, + { 0x24000000, 0xff000000, "ldptr.w", "r0:5,r5:5,so10:14<<2", 0, 0, 0, 0 }, + { 0x25000000, 0xff000000, "stptr.w", "r0:5,r5:5,so10:14<<2", 0, 0, 0, 0 }, + { 0x26000000, 0xff000000, "ldptr.d", "r0:5,r5:5,so10:14<<2", 0, 0, 0, 0 }, + { 0x27000000, 0xff000000, "stptr.d", "r0:5,r5:5,so10:14<<2", 0, 0, 0, 0 }, + { 0x28000000, 0xffc00000, "ld.b", "r0:5,r5:5,so10:12", 0, 0, 0, 0 }, + { 0x28400000, 0xffc00000, "ld.h", "r0:5,r5:5,so10:12", 0, 0, 0, 0 }, + { 0x28800000, 0xffc00000, "ld.w", "r0:5,r5:5,so10:12", 0, 0, 0, 0 }, + { 0x28c00000, 0xffc00000, "ld.d", "r0:5,r5:5,so10:12", 0, 0, 0, 0 }, + { 0x29000000, 0xffc00000, "st.b", "r0:5,r5:5,so10:12", 0, 0, 0, 0 }, + { 0x29400000, 0xffc00000, "st.h", "r0:5,r5:5,so10:12", 0, 0, 0, 0 }, + { 0x29800000, 0xffc00000, "st.w", "r0:5,r5:5,so10:12", 0, 0, 0, 0 }, + { 0x29c00000, 0xffc00000, "st.d", "r0:5,r5:5,so10:12", 0, 0, 0, 0 }, + { 0x2a000000, 0xffc00000, "ld.bu", "r0:5,r5:5,so10:12", 0, 0, 0, 0 }, + { 0x2a400000, 0xffc00000, "ld.hu", "r0:5,r5:5,so10:12", 0, 0, 0, 0 }, + { 0x2a800000, 0xffc00000, "ld.wu", "r0:5,r5:5,so10:12", 0, 0, 0, 0 }, + { 0x2ac00000, 0xffc00000, "preld", "u0:5,r5:5,so10:12", 0, 0, 0, 0 }, { 0x38000000, 0xffff8000, "ldx.b", "r0:5,r5:5,r10:5", 0, 0, 0, 0 }, { 0x38040000, 0xffff8000, "ldx.h", "r0:5,r5:5,r10:5", 0, 0, 0, 0 }, { 0x38080000, 0xffff8000, "ldx.w", "r0:5,r5:5,r10:5", 0, 0, 0, 0 }, @@ -767,35 +906,59 @@ static struct loongarch_opcode loongarch_load_store_opcodes[] = { 0x387e8000, 0xffff8000, "stle.h", "r0:5,r5:5,r10:5", 0, 0, 0, 0 }, { 0x387f0000, 0xffff8000, "stle.w", "r0:5,r5:5,r10:5", 0, 0, 0, 0 }, { 0x387f8000, 0xffff8000, "stle.d", "r0:5,r5:5,r10:5", 0, 0, 0, 0 }, - { 0 } /* Terminate the list. */ + { 0x2c000000, 0xffc00000, "vld", "v0:5,r5:5,s10:12", 0, 0, 0, 0}, + { 0x2c400000, 0xffc00000, "vst", "v0:5,r5:5,s10:12", 0, 0, 0, 0}, + { 0x2c800000, 0xffc00000, "xvld", "x0:5,r5:5,s10:12", 0, 0, 0, 0}, + { 0x2cc00000, 0xffc00000, "xvst", "x0:5,r5:5,s10:12", 0, 0, 0, 0}, + { 0x38400000, 0xffff8000, "vldx", "v0:5,r5:5,r10:5", 0, 0, 0, 0}, + { 0x38440000, 0xffff8000, "vstx", "v0:5,r5:5,r10:5", 0, 0, 0, 0}, + { 0x38480000, 0xffff8000, "xvldx", "x0:5,r5:5,r10:5", 0, 0, 0, 0}, + { 0x384c0000, 0xffff8000, "xvstx", "x0:5,r5:5,r10:5", 0, 0, 0, 0}, + { 0x30100000, 0xfff80000, "vldrepl.d", "v0:5,r5:5,s10:9<<3", 0, 0, 0, 0}, + { 0x30200000, 0xfff00000, "vldrepl.w", "v0:5,r5:5,s10:10<<2", 0, 0, 0, 0}, + { 0x30400000, 0xffe00000, "vldrepl.h", "v0:5,r5:5,s10:11<<1", 0, 0, 0, 0}, + { 0x30800000, 0xffc00000, "vldrepl.b", "v0:5,r5:5,s10:12", 0, 0, 0, 0}, + { 0x31100000, 0xfff80000, "vstelm.d", "v0:5,r5:5,s10:8<<3,u18:1", 0, 0, 0, 0}, + { 0x31200000, 0xfff00000, "vstelm.w", "v0:5,r5:5,s10:8<<2,u18:2", 0, 0, 0, 0}, + { 0x31400000, 0xffe00000, "vstelm.h", "v0:5,r5:5,s10:8<<1,u18:3", 0, 0, 0, 0}, + { 0x31800000, 0xffc00000, "vstelm.b", "v0:5,r5:5,s10:8,u18:4", 0, 0, 0, 0}, + { 0x32100000, 0xfff80000, "xvldrepl.d", "x0:5,r5:5,s10:9<<3", 0, 0, 0, 0}, + { 0x32200000, 0xfff00000, "xvldrepl.w", "x0:5,r5:5,s10:10<<2", 0, 0, 0, 0}, + { 0x32400000, 0xffe00000, "xvldrepl.h", "x0:5,r5:5,s10:11<<1", 0, 0, 0, 0}, + { 0x32800000, 0xffc00000, "xvldrepl.b", "x0:5,r5:5,s10:12", 0, 0, 0, 0}, + { 0x33100000, 0xfff00000, "xvstelm.d", "x0:5,r5:5,s10:8<<3,u18:2", 0, 0, 0, 0}, + { 0x33200000, 0xffe00000, "xvstelm.w", "x0:5,r5:5,s10:8<<2,u18:3", 0, 0, 0, 0}, + { 0x33400000, 0xffc00000, "xvstelm.h", "x0:5,r5:5,s10:8<<1,u18:4", 0, 0, 0, 0}, + { 0x33800000, 0xff800000, "xvstelm.b", "x0:5,r5:5,s10:8,u18:5", 0, 0, 0, 0}, + { 0, 0, 0, 0, 0, 0, 0, 0 } /* Terminate the list. */ }; static struct loongarch_opcode loongarch_single_float_load_store_opcodes[] = { /* match, mask, name, format, macro, include, exclude, pinfo. */ - { 0x2b000000, 0xffc00000, "fld.s", "f0:5,r5:5,s10:12", 0, 0, 0, 0 }, - { 0x2b400000, 0xffc00000, "fst.s", "f0:5,r5:5,s10:12", 0, 0, 0, 0 }, + { 0x2b000000, 0xffc00000, "fld.s", "f0:5,r5:5,so10:12", 0, 0, 0, 0 }, + { 0x2b400000, 0xffc00000, "fst.s", "f0:5,r5:5,so10:12", 0, 0, 0, 0 }, { 0x38300000, 0xffff8000, "fldx.s", "f0:5,r5:5,r10:5", 0, &LARCH_opts.ase_lp64, 0, 0 }, { 0x38380000, 0xffff8000, "fstx.s", "f0:5,r5:5,r10:5", 0, &LARCH_opts.ase_lp64, 0, 0 }, { 0x38740000, 0xffff8000, "fldgt.s", "f0:5,r5:5,r10:5", 0, &LARCH_opts.ase_lp64, 0, 0 }, { 0x38750000, 0xffff8000, "fldle.s", "f0:5,r5:5,r10:5", 0, &LARCH_opts.ase_lp64, 0, 0 }, { 0x38760000, 0xffff8000, "fstgt.s", "f0:5,r5:5,r10:5", 0, &LARCH_opts.ase_lp64, 0, 0 }, { 0x38770000, 0xffff8000, "fstle.s", "f0:5,r5:5,r10:5", 0, &LARCH_opts.ase_lp64, 0, 0 }, - { 0 } /* Terminate the list. */ + { 0, 0, 0, 0, 0, 0, 0, 0 } /* Terminate the list. */ }; static struct loongarch_opcode loongarch_double_float_load_store_opcodes[] = { /* match, mask, name, format, macro, include, exclude, pinfo. */ - { 0x2b800000, 0xffc00000, "fld.d", "f0:5,r5:5,s10:12", 0, 0, 0, 0 }, - { 0x2bc00000, 0xffc00000, "fst.d", "f0:5,r5:5,s10:12", 0, 0, 0, 0 }, + { 0x2b800000, 0xffc00000, "fld.d", "f0:5,r5:5,so10:12", 0, 0, 0, 0 }, + { 0x2bc00000, 0xffc00000, "fst.d", "f0:5,r5:5,so10:12", 0, 0, 0, 0 }, { 0x38340000, 0xffff8000, "fldx.d", "f0:5,r5:5,r10:5", 0, &LARCH_opts.ase_lp64, 0, 0 }, { 0x383c0000, 0xffff8000, "fstx.d", "f0:5,r5:5,r10:5", 0, &LARCH_opts.ase_lp64, 0, 0 }, { 0x38748000, 0xffff8000, "fldgt.d", "f0:5,r5:5,r10:5", 0, &LARCH_opts.ase_lp64, 0, 0 }, { 0x38758000, 0xffff8000, "fldle.d", "f0:5,r5:5,r10:5", 0, &LARCH_opts.ase_lp64, 0, 0 }, { 0x38768000, 0xffff8000, "fstgt.d", "f0:5,r5:5,r10:5", 0, &LARCH_opts.ase_lp64, 0, 0 }, { 0x38778000, 0xffff8000, "fstle.d", "f0:5,r5:5,r10:5", 0, &LARCH_opts.ase_lp64, 0, 0 }, - { 0 } /* Terminate the list. */ + { 0, 0, 0, 0, 0, 0, 0, 0 } /* Terminate the list. */ }; static struct loongarch_opcode loongarch_float_jmp_opcodes[] = @@ -804,28 +967,19 @@ static struct loongarch_opcode loongarch_float_jmp_opcodes[] = { 0x48000000, 0xfc000300, "bceqz", "c5:3,sb0:5|10:16<<2", 0, 0, 0, 0 }, { 0x0, 0x0, "bcnez", "c,la", "bcnez %1,%%b21(%2)", 0, 0, 0 }, { 0x48000100, 0xfc000300, "bcnez", "c5:3,sb0:5|10:16<<2", 0, 0, 0, 0 }, - { 0 } /* Terminate the list. */ + { 0, 0, 0, 0, 0, 0, 0, 0 } /* Terminate the list. */ }; static struct loongarch_opcode loongarch_jmp_opcodes[] = { /* match, mask, name, format, macro, include, exclude, pinfo. */ - { 0x0, 0x0, "bltz", "r,la", "bltz %1,%%b16(%2)", 0, 0, 0 }, - { 0x60000000, 0xfc00001f, "bltz", "r5:5,sb10:16<<2", 0, 0, 0, 0 }, - { 0x0, 0x0, "bgtz", "r,la", "bgtz %1,%%b16(%2)", 0, 0, 0 }, - { 0x60000000, 0xfc0003e0, "bgtz", "r0:5,sb10:16<<2", 0, 0, 0, 0 }, - { 0x0, 0x0, "bgez", "r,la", "bgez %1,%%b16(%2)", 0, 0, 0 }, - { 0x64000000, 0xfc00001f, "bgez", "r5:5,sb10:16<<2", 0, 0, 0, 0 }, - { 0x0, 0x0, "blez", "r,la", "blez %1,%%b16(%2)", 0, 0, 0 }, - { 0x64000000, 0xfc0003e0, "blez", "r0:5,sb10:16<<2", 0, 0, 0, 0 }, { 0x0, 0x0, "beqz", "r,la", "beqz %1,%%b21(%2)", 0, 0, 0 }, { 0x40000000, 0xfc000000, "beqz", "r5:5,sb0:5|10:16<<2", 0, 0, 0, 0 }, { 0x0, 0x0, "bnez", "r,la", "bnez %1,%%b21(%2)", 0, 0, 0 }, { 0x44000000, 0xfc000000, "bnez", "r5:5,sb0:5|10:16<<2", 0, 0, 0, 0 }, - { 0x0, 0x0, "jr", "r", "jirl $r0,%1,0", 0, 0, 0 }, - { 0x50000000, 0xfc000000, "b", "sb0:10|10:16<<2", 0, 0, 0, 0 }, + { 0x4c000000, 0xfc000000, "jirl", "r0:5,r5:5,so10:16<<2", 0, 0, 0, 0 }, { 0x0, 0x0, "b", "la", "b %%b26(%1)", 0, 0, 0 }, - { 0x4c000000, 0xfc000000, "jirl", "r0:5,r5:5,s10:16<<2", 0, 0, 0, 0 }, + { 0x50000000, 0xfc000000, "b", "sb0:10|10:16<<2", 0, 0, 0, 0 }, { 0x0, 0x0, "bl", "la", "bl %%b26(%1)", 0, 0, 0 }, { 0x54000000, 0xfc000000, "bl", "sb0:10|10:16<<2", 0, 0, 0, 0 }, { 0x0, 0x0, "beq", "r,r,la", "beq %1,%2,%%b16(%3)", 0, 0, 0 }, @@ -834,26 +988,1555 @@ static struct loongarch_opcode loongarch_jmp_opcodes[] = { 0x5c000000, 0xfc000000, "bne", "r5:5,r0:5,sb10:16<<2", 0, 0, 0, 0 }, { 0x0, 0x0, "blt", "r,r,la", "blt %1,%2,%%b16(%3)", 0, 0, 0 }, { 0x60000000, 0xfc000000, "blt", "r5:5,r0:5,sb10:16<<2", 0, 0, 0, 0 }, - { 0x0, 0x0, "bgt", "r,r,la", "bgt %1,%2,%%b16(%3)", 0, 0, 0 }, - { 0x60000000, 0xfc000000, "bgt", "r0:5,r5:5,sb10:16<<2", 0, 0, 0, 0 }, { 0x0, 0x0, "bge", "r,r,la", "bge %1,%2,%%b16(%3)", 0, 0, 0 }, { 0x64000000, 0xfc000000, "bge", "r5:5,r0:5,sb10:16<<2", 0, 0, 0, 0 }, - { 0x0, 0x0, "ble", "r,r,la", "ble %1,%2,%%b16(%3)", 0, 0, 0 }, - { 0x64000000, 0xfc000000, "ble", "r0:5,r5:5,sb10:16<<2", 0, 0, 0, 0 }, { 0x0, 0x0, "bltu", "r,r,la", "bltu %1,%2,%%b16(%3)", 0, 0, 0 }, { 0x68000000, 0xfc000000, "bltu", "r5:5,r0:5,sb10:16<<2", 0, 0, 0, 0 }, - { 0x0, 0x0, "bgtu", "r,r,la", "bgtu %1,%2,%%b16(%3)", 0, 0, 0 }, - { 0x68000000, 0xfc000000, "bgtu", "r0:5,r5:5,sb10:16<<2", 0, 0, 0, 0 }, { 0x0, 0x0, "bgeu", "r,r,la", "bgeu %1,%2,%%b16(%3)", 0, 0, 0 }, { 0x6c000000, 0xfc000000, "bgeu", "r5:5,r0:5,sb10:16<<2", 0, 0, 0, 0 }, - { 0x0, 0x0, "bleu", "r,r,la", "bleu %1,%2,%%b16(%3)", 0, 0, 0 }, - { 0x6c000000, 0xfc000000, "bleu", "r0:5,r5:5,sb10:16<<2", 0, 0, 0, 0 }, - { 0 } /* Terminate the list. */ + /* Jumps implemented with macros. */ + { 0x0, 0x0, "bgt", "r,r,la", "blt %2,%1,%%b16(%3)", 0, 0, 0 }, + { 0x0, 0x0, "bltz", "r,la", "blt %1,$r0,%%b16(%2)", 0, 0, 0 }, + { 0x0, 0x0, "bgtz", "r,la", "blt $r0,%1,%%b16(%2)", 0, 0, 0 }, + { 0x0, 0x0, "ble", "r,r,la", "bge %2,%1,%%b16(%3)", 0, 0, 0 }, + { 0x0, 0x0, "bgez", "r,la", "bge %1,$r0,%%b16(%2)", 0, 0, 0 }, + { 0x0, 0x0, "blez", "r,la", "bge $r0,%1,%%b16(%2)", 0, 0, 0 }, + { 0x0, 0x0, "bgtu", "r,r,la", "bltu %2,%1,%%b16(%3)", 0, 0, 0 }, + { 0x0, 0x0, "bleu", "r,r,la", "bgeu %2,%1,%%b16(%3)", 0, 0, 0 }, + { 0x0, 0x0, "jr", "r", "jirl $r0,%1,0", 0, 0, 0 }, + { 0x0, 0x0, "ret", "", "jirl $r0,$r1,0", 0, 0, 0 }, + { 0, 0, 0, 0, 0, 0, 0, 0 } /* Terminate the list. */ +}; + +static struct loongarch_opcode loongarch_lsx_opcodes[] = +{ +/* match, mask, name, format, macro, include, exclude, pinfo. */ + { 0x70000000, 0xffff8000, "vseq.b", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70008000, 0xffff8000, "vseq.h", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70010000, 0xffff8000, "vseq.w", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70018000, 0xffff8000, "vseq.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70020000, 0xffff8000, "vsle.b", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70028000, 0xffff8000, "vsle.h", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70030000, 0xffff8000, "vsle.w", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70038000, 0xffff8000, "vsle.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70040000, 0xffff8000, "vsle.bu", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70048000, 0xffff8000, "vsle.hu", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70050000, 0xffff8000, "vsle.wu", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70058000, 0xffff8000, "vsle.du", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70060000, 0xffff8000, "vslt.b", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70068000, 0xffff8000, "vslt.h", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70070000, 0xffff8000, "vslt.w", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70078000, 0xffff8000, "vslt.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70080000, 0xffff8000, "vslt.bu", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70088000, 0xffff8000, "vslt.hu", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70090000, 0xffff8000, "vslt.wu", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70098000, 0xffff8000, "vslt.du", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x700a0000, 0xffff8000, "vadd.b", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x700a8000, 0xffff8000, "vadd.h", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x700b0000, 0xffff8000, "vadd.w", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x700b8000, 0xffff8000, "vadd.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x700c0000, 0xffff8000, "vsub.b", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x700c8000, 0xffff8000, "vsub.h", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x700d0000, 0xffff8000, "vsub.w", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x700d8000, 0xffff8000, "vsub.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70460000, 0xffff8000, "vsadd.b", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70468000, 0xffff8000, "vsadd.h", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70470000, 0xffff8000, "vsadd.w", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70478000, 0xffff8000, "vsadd.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70480000, 0xffff8000, "vssub.b", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70488000, 0xffff8000, "vssub.h", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70490000, 0xffff8000, "vssub.w", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70498000, 0xffff8000, "vssub.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x704a0000, 0xffff8000, "vsadd.bu", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x704a8000, 0xffff8000, "vsadd.hu", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x704b0000, 0xffff8000, "vsadd.wu", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x704b8000, 0xffff8000, "vsadd.du", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x704c0000, 0xffff8000, "vssub.bu", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x704c8000, 0xffff8000, "vssub.hu", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x704d0000, 0xffff8000, "vssub.wu", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x704d8000, 0xffff8000, "vssub.du", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70540000, 0xffff8000, "vhaddw.h.b", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70548000, 0xffff8000, "vhaddw.w.h", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70550000, 0xffff8000, "vhaddw.d.w", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70558000, 0xffff8000, "vhaddw.q.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70560000, 0xffff8000, "vhsubw.h.b", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70568000, 0xffff8000, "vhsubw.w.h", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70570000, 0xffff8000, "vhsubw.d.w", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70578000, 0xffff8000, "vhsubw.q.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70580000, 0xffff8000, "vhaddw.hu.bu", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70588000, 0xffff8000, "vhaddw.wu.hu", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70590000, 0xffff8000, "vhaddw.du.wu", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70598000, 0xffff8000, "vhaddw.qu.du", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x705a0000, 0xffff8000, "vhsubw.hu.bu", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x705a8000, 0xffff8000, "vhsubw.wu.hu", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x705b0000, 0xffff8000, "vhsubw.du.wu", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x705b8000, 0xffff8000, "vhsubw.qu.du", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x705c0000, 0xffff8000, "vadda.b", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x705c8000, 0xffff8000, "vadda.h", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x705d0000, 0xffff8000, "vadda.w", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x705d8000, 0xffff8000, "vadda.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70600000, 0xffff8000, "vabsd.b", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70608000, 0xffff8000, "vabsd.h", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70610000, 0xffff8000, "vabsd.w", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70618000, 0xffff8000, "vabsd.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70620000, 0xffff8000, "vabsd.bu", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70628000, 0xffff8000, "vabsd.hu", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70630000, 0xffff8000, "vabsd.wu", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70638000, 0xffff8000, "vabsd.du", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70640000, 0xffff8000, "vavg.b", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70648000, 0xffff8000, "vavg.h", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70650000, 0xffff8000, "vavg.w", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70658000, 0xffff8000, "vavg.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70660000, 0xffff8000, "vavg.bu", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70668000, 0xffff8000, "vavg.hu", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70670000, 0xffff8000, "vavg.wu", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70678000, 0xffff8000, "vavg.du", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70680000, 0xffff8000, "vavgr.b", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70688000, 0xffff8000, "vavgr.h", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70690000, 0xffff8000, "vavgr.w", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70698000, 0xffff8000, "vavgr.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x706a0000, 0xffff8000, "vavgr.bu", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x706a8000, 0xffff8000, "vavgr.hu", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x706b0000, 0xffff8000, "vavgr.wu", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x706b8000, 0xffff8000, "vavgr.du", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70700000, 0xffff8000, "vmax.b", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70708000, 0xffff8000, "vmax.h", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70710000, 0xffff8000, "vmax.w", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70718000, 0xffff8000, "vmax.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70720000, 0xffff8000, "vmin.b", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70728000, 0xffff8000, "vmin.h", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70730000, 0xffff8000, "vmin.w", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70738000, 0xffff8000, "vmin.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70740000, 0xffff8000, "vmax.bu", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70748000, 0xffff8000, "vmax.hu", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70750000, 0xffff8000, "vmax.wu", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70758000, 0xffff8000, "vmax.du", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70760000, 0xffff8000, "vmin.bu", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70768000, 0xffff8000, "vmin.hu", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70770000, 0xffff8000, "vmin.wu", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70778000, 0xffff8000, "vmin.du", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70840000, 0xffff8000, "vmul.b", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70848000, 0xffff8000, "vmul.h", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70850000, 0xffff8000, "vmul.w", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70858000, 0xffff8000, "vmul.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70860000, 0xffff8000, "vmuh.b", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70868000, 0xffff8000, "vmuh.h", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70870000, 0xffff8000, "vmuh.w", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70878000, 0xffff8000, "vmuh.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70880000, 0xffff8000, "vmuh.bu", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70888000, 0xffff8000, "vmuh.hu", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70890000, 0xffff8000, "vmuh.wu", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70898000, 0xffff8000, "vmuh.du", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70a80000, 0xffff8000, "vmadd.b", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70a88000, 0xffff8000, "vmadd.h", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70a90000, 0xffff8000, "vmadd.w", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70a98000, 0xffff8000, "vmadd.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70aa0000, 0xffff8000, "vmsub.b", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70aa8000, 0xffff8000, "vmsub.h", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70ab0000, 0xffff8000, "vmsub.w", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70ab8000, 0xffff8000, "vmsub.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70e00000, 0xffff8000, "vdiv.b", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70e08000, 0xffff8000, "vdiv.h", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70e10000, 0xffff8000, "vdiv.w", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70e18000, 0xffff8000, "vdiv.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70e20000, 0xffff8000, "vmod.b", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70e28000, 0xffff8000, "vmod.h", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70e30000, 0xffff8000, "vmod.w", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70e38000, 0xffff8000, "vmod.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70e40000, 0xffff8000, "vdiv.bu", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70e48000, 0xffff8000, "vdiv.hu", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70e50000, 0xffff8000, "vdiv.wu", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70e58000, 0xffff8000, "vdiv.du", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70e60000, 0xffff8000, "vmod.bu", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70e68000, 0xffff8000, "vmod.hu", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70e70000, 0xffff8000, "vmod.wu", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70e78000, 0xffff8000, "vmod.du", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70e80000, 0xffff8000, "vsll.b", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70e88000, 0xffff8000, "vsll.h", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70e90000, 0xffff8000, "vsll.w", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70e98000, 0xffff8000, "vsll.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70ea0000, 0xffff8000, "vsrl.b", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70ea8000, 0xffff8000, "vsrl.h", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70eb0000, 0xffff8000, "vsrl.w", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70eb8000, 0xffff8000, "vsrl.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70ec0000, 0xffff8000, "vsra.b", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70ec8000, 0xffff8000, "vsra.h", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70ed0000, 0xffff8000, "vsra.w", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70ed8000, 0xffff8000, "vsra.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70ee0000, 0xffff8000, "vrotr.b", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70ee8000, 0xffff8000, "vrotr.h", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70ef0000, 0xffff8000, "vrotr.w", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70ef8000, 0xffff8000, "vrotr.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70f00000, 0xffff8000, "vsrlr.b", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70f08000, 0xffff8000, "vsrlr.h", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70f10000, 0xffff8000, "vsrlr.w", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70f18000, 0xffff8000, "vsrlr.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70f20000, 0xffff8000, "vsrar.b", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70f28000, 0xffff8000, "vsrar.h", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70f30000, 0xffff8000, "vsrar.w", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70f38000, 0xffff8000, "vsrar.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70f48000, 0xffff8000, "vsrln.b.h", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70f50000, 0xffff8000, "vsrln.h.w", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70f58000, 0xffff8000, "vsrln.w.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70f68000, 0xffff8000, "vsran.b.h", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70f70000, 0xffff8000, "vsran.h.w", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70f78000, 0xffff8000, "vsran.w.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70f88000, 0xffff8000, "vsrlrn.b.h", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70f90000, 0xffff8000, "vsrlrn.h.w", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70f98000, 0xffff8000, "vsrlrn.w.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70fa8000, 0xffff8000, "vsrarn.b.h", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70fb0000, 0xffff8000, "vsrarn.h.w", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70fb8000, 0xffff8000, "vsrarn.w.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70fc8000, 0xffff8000, "vssrln.b.h", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70fd0000, 0xffff8000, "vssrln.h.w", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70fd8000, 0xffff8000, "vssrln.w.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70fe8000, 0xffff8000, "vssran.b.h", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70ff0000, 0xffff8000, "vssran.h.w", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70ff8000, 0xffff8000, "vssran.w.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x71008000, 0xffff8000, "vssrlrn.b.h", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x71010000, 0xffff8000, "vssrlrn.h.w", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x71018000, 0xffff8000, "vssrlrn.w.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x71028000, 0xffff8000, "vssrarn.b.h", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x71030000, 0xffff8000, "vssrarn.h.w", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x71038000, 0xffff8000, "vssrarn.w.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x71048000, 0xffff8000, "vssrln.bu.h", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x71050000, 0xffff8000, "vssrln.hu.w", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x71058000, 0xffff8000, "vssrln.wu.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x71068000, 0xffff8000, "vssran.bu.h", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x71070000, 0xffff8000, "vssran.hu.w", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x71078000, 0xffff8000, "vssran.wu.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x71088000, 0xffff8000, "vssrlrn.bu.h", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x71090000, 0xffff8000, "vssrlrn.hu.w", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x71098000, 0xffff8000, "vssrlrn.wu.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x710a8000, 0xffff8000, "vssrarn.bu.h", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x710b0000, 0xffff8000, "vssrarn.hu.w", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x710b8000, 0xffff8000, "vssrarn.wu.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x710c0000, 0xffff8000, "vbitclr.b", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x710c8000, 0xffff8000, "vbitclr.h", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x710d0000, 0xffff8000, "vbitclr.w", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x710d8000, 0xffff8000, "vbitclr.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x710e0000, 0xffff8000, "vbitset.b", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x710e8000, 0xffff8000, "vbitset.h", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x710f0000, 0xffff8000, "vbitset.w", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x710f8000, 0xffff8000, "vbitset.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x71100000, 0xffff8000, "vbitrev.b", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x71108000, 0xffff8000, "vbitrev.h", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x71110000, 0xffff8000, "vbitrev.w", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x71118000, 0xffff8000, "vbitrev.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x71160000, 0xffff8000, "vpackev.b", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x71168000, 0xffff8000, "vpackev.h", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x71170000, 0xffff8000, "vpackev.w", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x71178000, 0xffff8000, "vpackev.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x71180000, 0xffff8000, "vpackod.b", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x71188000, 0xffff8000, "vpackod.h", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x71190000, 0xffff8000, "vpackod.w", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x71198000, 0xffff8000, "vpackod.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x711a0000, 0xffff8000, "vilvl.b", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x711a8000, 0xffff8000, "vilvl.h", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x711b0000, 0xffff8000, "vilvl.w", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x711b8000, 0xffff8000, "vilvl.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x711c0000, 0xffff8000, "vilvh.b", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x711c8000, 0xffff8000, "vilvh.h", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x711d0000, 0xffff8000, "vilvh.w", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x711d8000, 0xffff8000, "vilvh.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x711e0000, 0xffff8000, "vpickev.b", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x711e8000, 0xffff8000, "vpickev.h", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x711f0000, 0xffff8000, "vpickev.w", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x711f8000, 0xffff8000, "vpickev.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x71200000, 0xffff8000, "vpickod.b", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x71208000, 0xffff8000, "vpickod.h", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x71210000, 0xffff8000, "vpickod.w", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x71218000, 0xffff8000, "vpickod.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x71220000, 0xffff8000, "vreplve.b", "v0:5,v5:5,r10:5", 0, 0, 0, 0}, + { 0x71228000, 0xffff8000, "vreplve.h", "v0:5,v5:5,r10:5", 0, 0, 0, 0}, + { 0x71230000, 0xffff8000, "vreplve.w", "v0:5,v5:5,r10:5", 0, 0, 0, 0}, + { 0x71238000, 0xffff8000, "vreplve.d", "v0:5,v5:5,r10:5", 0, 0, 0, 0}, + { 0x71260000, 0xffff8000, "vand.v", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x71268000, 0xffff8000, "vor.v", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x71270000, 0xffff8000, "vxor.v", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x71278000, 0xffff8000, "vnor.v", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x71280000, 0xffff8000, "vandn.v", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x71288000, 0xffff8000, "vorn.v", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x712b0000, 0xffff8000, "vfrstp.b", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x712b8000, 0xffff8000, "vfrstp.h", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x712d0000, 0xffff8000, "vadd.q", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x712d8000, 0xffff8000, "vsub.q", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x712e0000, 0xffff8000, "vsigncov.b", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x712e8000, 0xffff8000, "vsigncov.h", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x712f0000, 0xffff8000, "vsigncov.w", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x712f8000, 0xffff8000, "vsigncov.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x71308000, 0xffff8000, "vfadd.s", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x71310000, 0xffff8000, "vfadd.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x71328000, 0xffff8000, "vfsub.s", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x71330000, 0xffff8000, "vfsub.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x71388000, 0xffff8000, "vfmul.s", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x71390000, 0xffff8000, "vfmul.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x713a8000, 0xffff8000, "vfdiv.s", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x713b0000, 0xffff8000, "vfdiv.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x713c8000, 0xffff8000, "vfmax.s", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x713d0000, 0xffff8000, "vfmax.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x713e8000, 0xffff8000, "vfmin.s", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x713f0000, 0xffff8000, "vfmin.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x71408000, 0xffff8000, "vfmaxa.s", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x71410000, 0xffff8000, "vfmaxa.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x71428000, 0xffff8000, "vfmina.s", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x71430000, 0xffff8000, "vfmina.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x71460000, 0xffff8000, "vfcvt.h.s", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x71468000, 0xffff8000, "vfcvt.s.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x71480000, 0xffff8000, "vffint.s.l", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x71498000, 0xffff8000, "vftint.w.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x714a0000, 0xffff8000, "vftintrm.w.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x714a8000, 0xffff8000, "vftintrp.w.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x714b0000, 0xffff8000, "vftintrz.w.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x714b8000, 0xffff8000, "vftintrne.w.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x717a8000, 0xffff8000, "vshuf.h", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x717b0000, 0xffff8000, "vshuf.w", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x717b8000, 0xffff8000, "vshuf.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x72800000, 0xffff8000, "vseqi.b", "v0:5,v5:5,s10:5", 0, 0, 0, 0}, + { 0x72808000, 0xffff8000, "vseqi.h", "v0:5,v5:5,s10:5", 0, 0, 0, 0}, + { 0x72810000, 0xffff8000, "vseqi.w", "v0:5,v5:5,s10:5", 0, 0, 0, 0}, + { 0x72818000, 0xffff8000, "vseqi.d", "v0:5,v5:5,s10:5", 0, 0, 0, 0}, + { 0x72820000, 0xffff8000, "vslei.b", "v0:5,v5:5,s10:5", 0, 0, 0, 0}, + { 0x72828000, 0xffff8000, "vslei.h", "v0:5,v5:5,s10:5", 0, 0, 0, 0}, + { 0x72830000, 0xffff8000, "vslei.w", "v0:5,v5:5,s10:5", 0, 0, 0, 0}, + { 0x72838000, 0xffff8000, "vslei.d", "v0:5,v5:5,s10:5", 0, 0, 0, 0}, + { 0x72840000, 0xffff8000, "vslei.bu", "v0:5,v5:5,u10:5", 0, 0, 0, 0}, + { 0x72848000, 0xffff8000, "vslei.hu", "v0:5,v5:5,u10:5", 0, 0, 0, 0}, + { 0x72850000, 0xffff8000, "vslei.wu", "v0:5,v5:5,u10:5", 0, 0, 0, 0}, + { 0x72858000, 0xffff8000, "vslei.du", "v0:5,v5:5,u10:5", 0, 0, 0, 0}, + { 0x72860000, 0xffff8000, "vslti.b", "v0:5,v5:5,s10:5", 0, 0, 0, 0}, + { 0x72868000, 0xffff8000, "vslti.h", "v0:5,v5:5,s10:5", 0, 0, 0, 0}, + { 0x72870000, 0xffff8000, "vslti.w", "v0:5,v5:5,s10:5", 0, 0, 0, 0}, + { 0x72878000, 0xffff8000, "vslti.d", "v0:5,v5:5,s10:5", 0, 0, 0, 0}, + { 0x72880000, 0xffff8000, "vslti.bu", "v0:5,v5:5,u10:5", 0, 0, 0, 0}, + { 0x72888000, 0xffff8000, "vslti.hu", "v0:5,v5:5,u10:5", 0, 0, 0, 0}, + { 0x72890000, 0xffff8000, "vslti.wu", "v0:5,v5:5,u10:5", 0, 0, 0, 0}, + { 0x72898000, 0xffff8000, "vslti.du", "v0:5,v5:5,u10:5", 0, 0, 0, 0}, + { 0x728a0000, 0xffff8000, "vaddi.bu", "v0:5,v5:5,u10:5", 0, 0, 0, 0}, + { 0x728a8000, 0xffff8000, "vaddi.hu", "v0:5,v5:5,u10:5", 0, 0, 0, 0}, + { 0x728b0000, 0xffff8000, "vaddi.wu", "v0:5,v5:5,u10:5", 0, 0, 0, 0}, + { 0x728b8000, 0xffff8000, "vaddi.du", "v0:5,v5:5,u10:5", 0, 0, 0, 0}, + { 0x728c0000, 0xffff8000, "vsubi.bu", "v0:5,v5:5,u10:5", 0, 0, 0, 0}, + { 0x728c8000, 0xffff8000, "vsubi.hu", "v0:5,v5:5,u10:5", 0, 0, 0, 0}, + { 0x728d0000, 0xffff8000, "vsubi.wu", "v0:5,v5:5,u10:5", 0, 0, 0, 0}, + { 0x728d8000, 0xffff8000, "vsubi.du", "v0:5,v5:5,u10:5", 0, 0, 0, 0}, + { 0x728e0000, 0xffff8000, "vbsll.v", "v0:5,v5:5,u10:5", 0, 0, 0, 0}, + { 0x728e8000, 0xffff8000, "vbsrl.v", "v0:5,v5:5,u10:5", 0, 0, 0, 0}, + { 0x72900000, 0xffff8000, "vmaxi.b", "v0:5,v5:5,s10:5", 0, 0, 0, 0}, + { 0x72908000, 0xffff8000, "vmaxi.h", "v0:5,v5:5,s10:5", 0, 0, 0, 0}, + { 0x72910000, 0xffff8000, "vmaxi.w", "v0:5,v5:5,s10:5", 0, 0, 0, 0}, + { 0x72918000, 0xffff8000, "vmaxi.d", "v0:5,v5:5,s10:5", 0, 0, 0, 0}, + { 0x72920000, 0xffff8000, "vmini.b", "v0:5,v5:5,s10:5", 0, 0, 0, 0}, + { 0x72928000, 0xffff8000, "vmini.h", "v0:5,v5:5,s10:5", 0, 0, 0, 0}, + { 0x72930000, 0xffff8000, "vmini.w", "v0:5,v5:5,s10:5", 0, 0, 0, 0}, + { 0x72938000, 0xffff8000, "vmini.d", "v0:5,v5:5,s10:5", 0, 0, 0, 0}, + { 0x72940000, 0xffff8000, "vmaxi.bu", "v0:5,v5:5,u10:5", 0, 0, 0, 0}, + { 0x72948000, 0xffff8000, "vmaxi.hu", "v0:5,v5:5,u10:5", 0, 0, 0, 0}, + { 0x72950000, 0xffff8000, "vmaxi.wu", "v0:5,v5:5,u10:5", 0, 0, 0, 0}, + { 0x72958000, 0xffff8000, "vmaxi.du", "v0:5,v5:5,u10:5", 0, 0, 0, 0}, + { 0x72960000, 0xffff8000, "vmini.bu", "v0:5,v5:5,u10:5", 0, 0, 0, 0}, + { 0x72968000, 0xffff8000, "vmini.hu", "v0:5,v5:5,u10:5", 0, 0, 0, 0}, + { 0x72970000, 0xffff8000, "vmini.wu", "v0:5,v5:5,u10:5", 0, 0, 0, 0}, + { 0x72978000, 0xffff8000, "vmini.du", "v0:5,v5:5,u10:5", 0, 0, 0, 0}, + { 0x729a0000, 0xffff8000, "vfrstpi.b", "v0:5,v5:5,u10:5", 0, 0, 0, 0}, + { 0x729a8000, 0xffff8000, "vfrstpi.h", "v0:5,v5:5,u10:5", 0, 0, 0, 0}, + { 0x729c0000, 0xfffffc00, "vclo.b", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729c0400, 0xfffffc00, "vclo.h", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729c0800, 0xfffffc00, "vclo.w", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729c0c00, 0xfffffc00, "vclo.d", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729c1000, 0xfffffc00, "vclz.b", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729c1400, 0xfffffc00, "vclz.h", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729c1800, 0xfffffc00, "vclz.w", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729c1c00, 0xfffffc00, "vclz.d", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729c2000, 0xfffffc00, "vpcnt.b", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729c2400, 0xfffffc00, "vpcnt.h", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729c2800, 0xfffffc00, "vpcnt.w", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729c2c00, 0xfffffc00, "vpcnt.d", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729c3000, 0xfffffc00, "vneg.b", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729c3400, 0xfffffc00, "vneg.h", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729c3800, 0xfffffc00, "vneg.w", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729c3c00, 0xfffffc00, "vneg.d", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729c4000, 0xfffffc00, "vmskltz.b", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729c4400, 0xfffffc00, "vmskltz.h", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729c4800, 0xfffffc00, "vmskltz.w", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729c4c00, 0xfffffc00, "vmskltz.d", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729c5000, 0xfffffc00, "vmskgez.b", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729c6000, 0xfffffc00, "vmsknz.b", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729c9800, 0xfffffc18, "vseteqz.v", "c0:3,v5:5", 0, 0, 0, 0}, + { 0x729c9c00, 0xfffffc18, "vsetnez.v", "c0:3,v5:5", 0, 0, 0, 0}, + { 0x729ca000, 0xfffffc18, "vsetanyeqz.b", "c0:3,v5:5", 0, 0, 0, 0}, + { 0x729ca400, 0xfffffc18, "vsetanyeqz.h", "c0:3,v5:5", 0, 0, 0, 0}, + { 0x729ca800, 0xfffffc18, "vsetanyeqz.w", "c0:3,v5:5", 0, 0, 0, 0}, + { 0x729cac00, 0xfffffc18, "vsetanyeqz.d", "c0:3,v5:5", 0, 0, 0, 0}, + { 0x729cb000, 0xfffffc18, "vsetallnez.b", "c0:3,v5:5", 0, 0, 0, 0}, + { 0x729cb400, 0xfffffc18, "vsetallnez.h", "c0:3,v5:5", 0, 0, 0, 0}, + { 0x729cb800, 0xfffffc18, "vsetallnez.w", "c0:3,v5:5", 0, 0, 0, 0}, + { 0x729cbc00, 0xfffffc18, "vsetallnez.d", "c0:3,v5:5", 0, 0, 0, 0}, + { 0x729cc400, 0xfffffc00, "vflogb.s", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729cc800, 0xfffffc00, "vflogb.d", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729cd400, 0xfffffc00, "vfclass.s", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729cd800, 0xfffffc00, "vfclass.d", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729ce400, 0xfffffc00, "vfsqrt.s", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729ce800, 0xfffffc00, "vfsqrt.d", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729cf400, 0xfffffc00, "vfrecip.s", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729cf800, 0xfffffc00, "vfrecip.d", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729d0400, 0xfffffc00, "vfrsqrt.s", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729d0800, 0xfffffc00, "vfrsqrt.d", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729d3400, 0xfffffc00, "vfrint.s", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729d3800, 0xfffffc00, "vfrint.d", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729d4400, 0xfffffc00, "vfrintrm.s", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729d4800, 0xfffffc00, "vfrintrm.d", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729d5400, 0xfffffc00, "vfrintrp.s", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729d5800, 0xfffffc00, "vfrintrp.d", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729d6400, 0xfffffc00, "vfrintrz.s", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729d6800, 0xfffffc00, "vfrintrz.d", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729d7400, 0xfffffc00, "vfrintrne.s", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729d7800, 0xfffffc00, "vfrintrne.d", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729de800, 0xfffffc00, "vfcvtl.s.h", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729dec00, 0xfffffc00, "vfcvth.s.h", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729df000, 0xfffffc00, "vfcvtl.d.s", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729df400, 0xfffffc00, "vfcvth.d.s", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729e0000, 0xfffffc00, "vffint.s.w", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729e0400, 0xfffffc00, "vffint.s.wu", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729e0800, 0xfffffc00, "vffint.d.l", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729e0c00, 0xfffffc00, "vffint.d.lu", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729e1000, 0xfffffc00, "vffintl.d.w", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729e1400, 0xfffffc00, "vffinth.d.w", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729e3000, 0xfffffc00, "vftint.w.s", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729e3400, 0xfffffc00, "vftint.l.d", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729e3800, 0xfffffc00, "vftintrm.w.s", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729e3c00, 0xfffffc00, "vftintrm.l.d", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729e4000, 0xfffffc00, "vftintrp.w.s", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729e4400, 0xfffffc00, "vftintrp.l.d", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729e4800, 0xfffffc00, "vftintrz.w.s", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729e4c00, 0xfffffc00, "vftintrz.l.d", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729e5000, 0xfffffc00, "vftintrne.w.s", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729e5400, 0xfffffc00, "vftintrne.l.d", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729e5800, 0xfffffc00, "vftint.wu.s", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729e5c00, 0xfffffc00, "vftint.lu.d", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729e7000, 0xfffffc00, "vftintrz.wu.s", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729e7400, 0xfffffc00, "vftintrz.lu.d", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729e8000, 0xfffffc00, "vftintl.l.s", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729e8400, 0xfffffc00, "vftinth.l.s", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729e8800, 0xfffffc00, "vftintrml.l.s", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729e8c00, 0xfffffc00, "vftintrmh.l.s", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729e9000, 0xfffffc00, "vftintrpl.l.s", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729e9400, 0xfffffc00, "vftintrph.l.s", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729e9800, 0xfffffc00, "vftintrzl.l.s", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729e9c00, 0xfffffc00, "vftintrzh.l.s", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729ea000, 0xfffffc00, "vftintrnel.l.s", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729ea400, 0xfffffc00, "vftintrneh.l.s", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729ee000, 0xfffffc00, "vexth.h.b", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729ee400, 0xfffffc00, "vexth.w.h", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729ee800, 0xfffffc00, "vexth.d.w", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729eec00, 0xfffffc00, "vexth.q.d", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729ef000, 0xfffffc00, "vexth.hu.bu", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729ef400, 0xfffffc00, "vexth.wu.hu", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729ef800, 0xfffffc00, "vexth.du.wu", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729efc00, 0xfffffc00, "vexth.qu.du", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729f0000, 0xfffffc00, "vreplgr2vr.b", "v0:5,r5:5", 0, 0, 0, 0}, + { 0x729f0400, 0xfffffc00, "vreplgr2vr.h", "v0:5,r5:5", 0, 0, 0, 0}, + { 0x729f0800, 0xfffffc00, "vreplgr2vr.w", "v0:5,r5:5", 0, 0, 0, 0}, + { 0x729f0c00, 0xfffffc00, "vreplgr2vr.d", "v0:5,r5:5", 0, 0, 0, 0}, + { 0x72a02000, 0xffffe000, "vrotri.b", "v0:5,v5:5,u10:3", 0, 0, 0, 0}, + { 0x72a04000, 0xffffc000, "vrotri.h", "v0:5,v5:5,u10:4", 0, 0, 0, 0}, + { 0x72a08000, 0xffff8000, "vrotri.w", "v0:5,v5:5,u10:5", 0, 0, 0, 0}, + { 0x72a10000, 0xffff0000, "vrotri.d", "v0:5,v5:5,u10:6", 0, 0, 0, 0}, + { 0x72a42000, 0xffffe000, "vsrlri.b", "v0:5,v5:5,u10:3", 0, 0, 0, 0}, + { 0x72a44000, 0xffffc000, "vsrlri.h", "v0:5,v5:5,u10:4", 0, 0, 0, 0}, + { 0x72a48000, 0xffff8000, "vsrlri.w", "v0:5,v5:5,u10:5", 0, 0, 0, 0}, + { 0x72a50000, 0xffff0000, "vsrlri.d", "v0:5,v5:5,u10:6", 0, 0, 0, 0}, + { 0x72a82000, 0xffffe000, "vsrari.b", "v0:5,v5:5,u10:3", 0, 0, 0, 0}, + { 0x72a84000, 0xffffc000, "vsrari.h", "v0:5,v5:5,u10:4", 0, 0, 0, 0}, + { 0x72a88000, 0xffff8000, "vsrari.w", "v0:5,v5:5,u10:5", 0, 0, 0, 0}, + { 0x72a90000, 0xffff0000, "vsrari.d", "v0:5,v5:5,u10:6", 0, 0, 0, 0}, + { 0x72eb8000, 0xffffc000, "vinsgr2vr.b", "v0:5,r5:5,u10:4", 0, 0, 0, 0}, + { 0x72ebc000, 0xffffe000, "vinsgr2vr.h", "v0:5,r5:5,u10:3", 0, 0, 0, 0}, + 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"v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x702e8000, 0xffff8000, "vaddwev.w.hu", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x702f0000, 0xffff8000, "vaddwev.d.wu", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x702f8000, 0xffff8000, "vaddwev.q.du", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x703e0000, 0xffff8000, "vaddwev.h.bu.b", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x703e8000, 0xffff8000, "vaddwev.w.hu.h", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x703f0000, 0xffff8000, "vaddwev.d.wu.w", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x703f8000, 0xffff8000, "vaddwev.q.du.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70220000, 0xffff8000, "vaddwod.h.b", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70228000, 0xffff8000, "vaddwod.w.h", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70230000, 0xffff8000, "vaddwod.d.w", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70238000, 0xffff8000, "vaddwod.q.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70320000, 0xffff8000, "vaddwod.h.bu", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70328000, 0xffff8000, "vaddwod.w.hu", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70330000, 0xffff8000, "vaddwod.d.wu", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70338000, 0xffff8000, "vaddwod.q.du", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70400000, 0xffff8000, "vaddwod.h.bu.b", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70408000, 0xffff8000, "vaddwod.w.hu.h", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70410000, 0xffff8000, "vaddwod.d.wu.w", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70418000, 0xffff8000, "vaddwod.q.du.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70ac0000, 0xffff8000, "vmaddwev.h.b", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70ac8000, 0xffff8000, "vmaddwev.w.h", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70ad0000, 0xffff8000, "vmaddwev.d.w", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70ad8000, 0xffff8000, "vmaddwev.q.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70b40000, 0xffff8000, "vmaddwev.h.bu", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70b48000, 0xffff8000, "vmaddwev.w.hu", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70b50000, 0xffff8000, "vmaddwev.d.wu", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70b58000, 0xffff8000, "vmaddwev.q.du", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70bc0000, 0xffff8000, "vmaddwev.h.bu.b", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70bc8000, 0xffff8000, "vmaddwev.w.hu.h", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70bd0000, 0xffff8000, "vmaddwev.d.wu.w", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70bd8000, 0xffff8000, "vmaddwev.q.du.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70ae0000, 0xffff8000, "vmaddwod.h.b", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70ae8000, 0xffff8000, "vmaddwod.w.h", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70af0000, 0xffff8000, "vmaddwod.d.w", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70af8000, 0xffff8000, "vmaddwod.q.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70b60000, 0xffff8000, "vmaddwod.h.bu", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70b68000, 0xffff8000, "vmaddwod.w.hu", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70b70000, 0xffff8000, "vmaddwod.d.wu", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70b78000, 0xffff8000, "vmaddwod.q.du", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70be0000, 0xffff8000, "vmaddwod.h.bu.b", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70be8000, 0xffff8000, "vmaddwod.w.hu.h", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70bf0000, 0xffff8000, "vmaddwod.d.wu.w", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70bf8000, 0xffff8000, "vmaddwod.q.du.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70900000, 0xffff8000, "vmulwev.h.b", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70908000, 0xffff8000, "vmulwev.w.h", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70910000, 0xffff8000, "vmulwev.d.w", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70918000, 0xffff8000, "vmulwev.q.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70980000, 0xffff8000, "vmulwev.h.bu", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70988000, 0xffff8000, "vmulwev.w.hu", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70990000, 0xffff8000, "vmulwev.d.wu", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70998000, 0xffff8000, "vmulwev.q.du", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70a00000, 0xffff8000, "vmulwev.h.bu.b", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70a08000, 0xffff8000, "vmulwev.w.hu.h", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70a10000, 0xffff8000, "vmulwev.d.wu.w", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70a18000, 0xffff8000, "vmulwev.q.du.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70920000, 0xffff8000, "vmulwod.h.b", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70928000, 0xffff8000, "vmulwod.w.h", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70930000, 0xffff8000, "vmulwod.d.w", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70938000, 0xffff8000, "vmulwod.q.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x709a0000, 0xffff8000, "vmulwod.h.bu", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x709a8000, 0xffff8000, "vmulwod.w.hu", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x709b0000, 0xffff8000, "vmulwod.d.wu", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x709b8000, 0xffff8000, "vmulwod.q.du", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70a20000, 0xffff8000, "vmulwod.h.bu.b", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70a28000, 0xffff8000, "vmulwod.w.hu.h", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70a30000, 0xffff8000, "vmulwod.d.wu.w", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70a38000, 0xffff8000, "vmulwod.q.du.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70200000, 0xffff8000, "vsubwev.h.b", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70208000, 0xffff8000, "vsubwev.w.h", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70210000, 0xffff8000, "vsubwev.d.w", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70218000, 0xffff8000, "vsubwev.q.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70300000, 0xffff8000, "vsubwev.h.bu", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70308000, 0xffff8000, "vsubwev.w.hu", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70310000, 0xffff8000, "vsubwev.d.wu", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70318000, 0xffff8000, "vsubwev.q.du", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70240000, 0xffff8000, "vsubwod.h.b", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70248000, 0xffff8000, "vsubwod.w.h", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70250000, 0xffff8000, "vsubwod.d.w", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70258000, 0xffff8000, "vsubwod.q.d", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70340000, 0xffff8000, "vsubwod.h.bu", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70348000, 0xffff8000, "vsubwod.w.hu", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70350000, 0xffff8000, "vsubwod.d.wu", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0x70358000, 0xffff8000, "vsubwod.q.du", "v0:5,v5:5,v10:5", 0, 0, 0, 0 }, + { 0, 0, "vrepli.d", "v,s0:10", "vldi %1,((%2)&0x3ff)|0xc00", 0, 0, 0}, + { 0, 0, "vrepli.h", "v,s0:10", "vldi %1,((%2)&0x3ff)|0x400", 0, 0, 0}, + { 0, 0, "vrepli.w", "v,s0:10", "vldi %1,((%2)&0x3ff)|0x800", 0, 0, 0}, + { 0x73e00000, 0xfffc0000, "vldi", "v0:5,s5:13", 0, 0, 0, 0}, + { 0x73e40000, 0xfffc0000, "vpermi.w", "v0:5,v5:5,u10:8", 0, 0, 0, 0}, + { 0, 0, 0, 0, 0, 0, 0, 0 } /* Terminate the list. */ +}; + +static struct loongarch_opcode loongarch_lasx_opcodes[] = +{ +/* match, mask, name, format, macro, include, exclude, pinfo. */ + { 0x74000000, 0xffff8000, "xvseq.b", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74008000, 0xffff8000, "xvseq.h", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74010000, 0xffff8000, "xvseq.w", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74018000, 0xffff8000, "xvseq.d", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74020000, 0xffff8000, "xvsle.b", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74028000, 0xffff8000, "xvsle.h", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74030000, 0xffff8000, "xvsle.w", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74038000, 0xffff8000, "xvsle.d", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74040000, 0xffff8000, "xvsle.bu", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74048000, 0xffff8000, "xvsle.hu", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74050000, 0xffff8000, "xvsle.wu", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74058000, 0xffff8000, "xvsle.du", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74060000, 0xffff8000, "xvslt.b", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74068000, 0xffff8000, "xvslt.h", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74070000, 0xffff8000, "xvslt.w", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74078000, 0xffff8000, "xvslt.d", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74080000, 0xffff8000, "xvslt.bu", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74088000, 0xffff8000, "xvslt.hu", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74090000, 0xffff8000, "xvslt.wu", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74098000, 0xffff8000, "xvslt.du", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x740a0000, 0xffff8000, "xvadd.b", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x740a8000, 0xffff8000, "xvadd.h", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x740b0000, 0xffff8000, "xvadd.w", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x740b8000, 0xffff8000, "xvadd.d", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x740c0000, 0xffff8000, "xvsub.b", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x740c8000, 0xffff8000, "xvsub.h", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x740d0000, 0xffff8000, "xvsub.w", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x740d8000, 0xffff8000, "xvsub.d", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74460000, 0xffff8000, "xvsadd.b", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74468000, 0xffff8000, "xvsadd.h", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74470000, 0xffff8000, "xvsadd.w", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74478000, 0xffff8000, "xvsadd.d", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74480000, 0xffff8000, "xvssub.b", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74488000, 0xffff8000, "xvssub.h", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74490000, 0xffff8000, "xvssub.w", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74498000, 0xffff8000, "xvssub.d", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x744a0000, 0xffff8000, "xvsadd.bu", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x744a8000, 0xffff8000, "xvsadd.hu", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x744b0000, 0xffff8000, "xvsadd.wu", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x744b8000, 0xffff8000, "xvsadd.du", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x744c0000, 0xffff8000, "xvssub.bu", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x744c8000, 0xffff8000, "xvssub.hu", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x744d0000, 0xffff8000, "xvssub.wu", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x744d8000, 0xffff8000, "xvssub.du", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74540000, 0xffff8000, "xvhaddw.h.b", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74548000, 0xffff8000, "xvhaddw.w.h", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74550000, 0xffff8000, "xvhaddw.d.w", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74558000, 0xffff8000, "xvhaddw.q.d", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74560000, 0xffff8000, "xvhsubw.h.b", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74568000, 0xffff8000, "xvhsubw.w.h", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74570000, 0xffff8000, "xvhsubw.d.w", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74578000, 0xffff8000, "xvhsubw.q.d", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74580000, 0xffff8000, "xvhaddw.hu.bu", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74588000, 0xffff8000, "xvhaddw.wu.hu", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74590000, 0xffff8000, "xvhaddw.du.wu", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74598000, 0xffff8000, "xvhaddw.qu.du", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x745a0000, 0xffff8000, "xvhsubw.hu.bu", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x745a8000, 0xffff8000, "xvhsubw.wu.hu", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x745b0000, 0xffff8000, "xvhsubw.du.wu", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x745b8000, 0xffff8000, "xvhsubw.qu.du", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x741e0000, 0xffff8000, "xvaddwev.h.b", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x741e8000, 0xffff8000, "xvaddwev.w.h", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x741f0000, 0xffff8000, "xvaddwev.d.w", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x741f8000, 0xffff8000, "xvaddwev.q.d", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x742e0000, 0xffff8000, "xvaddwev.h.bu", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x742e8000, 0xffff8000, "xvaddwev.w.hu", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x742f0000, 0xffff8000, "xvaddwev.d.wu", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x742f8000, 0xffff8000, "xvaddwev.q.du", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x743e0000, 0xffff8000, "xvaddwev.h.bu.b", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x743e8000, 0xffff8000, "xvaddwev.w.hu.h", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x743f0000, 0xffff8000, "xvaddwev.d.wu.w", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x743f8000, 0xffff8000, "xvaddwev.q.du.d", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74220000, 0xffff8000, "xvaddwod.h.b", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74228000, 0xffff8000, "xvaddwod.w.h", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74230000, 0xffff8000, "xvaddwod.d.w", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74238000, 0xffff8000, "xvaddwod.q.d", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74320000, 0xffff8000, "xvaddwod.h.bu", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74328000, 0xffff8000, "xvaddwod.w.hu", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74330000, 0xffff8000, "xvaddwod.d.wu", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 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{ 0x74e60000, 0xffff8000, "xvmod.bu", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74e68000, 0xffff8000, "xvmod.hu", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74e70000, 0xffff8000, "xvmod.wu", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74e78000, 0xffff8000, "xvmod.du", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74e80000, 0xffff8000, "xvsll.b", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74e88000, 0xffff8000, "xvsll.h", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74e90000, 0xffff8000, "xvsll.w", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74e98000, 0xffff8000, "xvsll.d", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74ea0000, 0xffff8000, "xvsrl.b", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74ea8000, 0xffff8000, "xvsrl.h", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74eb0000, 0xffff8000, "xvsrl.w", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74eb8000, 0xffff8000, "xvsrl.d", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74ec0000, 0xffff8000, "xvsra.b", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74ec8000, 0xffff8000, "xvsra.h", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74ed0000, 0xffff8000, "xvsra.w", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74ed8000, 0xffff8000, "xvsra.d", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74ee0000, 0xffff8000, "xvrotr.b", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74ee8000, 0xffff8000, "xvrotr.h", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74ef0000, 0xffff8000, "xvrotr.w", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74ef8000, 0xffff8000, "xvrotr.d", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74f00000, 0xffff8000, "xvsrlr.b", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74f08000, 0xffff8000, "xvsrlr.h", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74f10000, 0xffff8000, "xvsrlr.w", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74f18000, 0xffff8000, "xvsrlr.d", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74f20000, 0xffff8000, "xvsrar.b", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74f28000, 0xffff8000, "xvsrar.h", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74f30000, 0xffff8000, "xvsrar.w", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74f38000, 0xffff8000, "xvsrar.d", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74f48000, 0xffff8000, "xvsrln.b.h", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74f50000, 0xffff8000, "xvsrln.h.w", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74f58000, 0xffff8000, "xvsrln.w.d", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74f68000, 0xffff8000, "xvsran.b.h", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74f70000, 0xffff8000, "xvsran.h.w", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74f78000, 0xffff8000, "xvsran.w.d", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74f88000, 0xffff8000, "xvsrlrn.b.h", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74f90000, 0xffff8000, "xvsrlrn.h.w", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74f98000, 0xffff8000, "xvsrlrn.w.d", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74fa8000, 0xffff8000, "xvsrarn.b.h", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74fb0000, 0xffff8000, "xvsrarn.h.w", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74fb8000, 0xffff8000, "xvsrarn.w.d", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74fc8000, 0xffff8000, "xvssrln.b.h", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74fd0000, 0xffff8000, "xvssrln.h.w", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74fd8000, 0xffff8000, "xvssrln.w.d", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74fe8000, 0xffff8000, "xvssran.b.h", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74ff0000, 0xffff8000, "xvssran.h.w", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x74ff8000, 0xffff8000, "xvssran.w.d", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x75008000, 0xffff8000, "xvssrlrn.b.h", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x75010000, 0xffff8000, "xvssrlrn.h.w", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x75018000, 0xffff8000, "xvssrlrn.w.d", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x75028000, 0xffff8000, "xvssrarn.b.h", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x75030000, 0xffff8000, "xvssrarn.h.w", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x75038000, 0xffff8000, "xvssrarn.w.d", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x75048000, 0xffff8000, "xvssrln.bu.h", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x75050000, 0xffff8000, "xvssrln.hu.w", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x75058000, 0xffff8000, "xvssrln.wu.d", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x75068000, 0xffff8000, "xvssran.bu.h", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x75070000, 0xffff8000, "xvssran.hu.w", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x75078000, 0xffff8000, "xvssran.wu.d", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x75088000, 0xffff8000, "xvssrlrn.bu.h", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x75090000, 0xffff8000, "xvssrlrn.hu.w", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x75098000, 0xffff8000, "xvssrlrn.wu.d", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x750a8000, 0xffff8000, "xvssrarn.bu.h", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x750b0000, 0xffff8000, "xvssrarn.hu.w", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x750b8000, 0xffff8000, "xvssrarn.wu.d", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x750c0000, 0xffff8000, "xvbitclr.b", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x750c8000, 0xffff8000, "xvbitclr.h", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x750d0000, 0xffff8000, "xvbitclr.w", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x750d8000, 0xffff8000, "xvbitclr.d", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x750e0000, 0xffff8000, "xvbitset.b", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x750e8000, 0xffff8000, "xvbitset.h", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x750f0000, 0xffff8000, "xvbitset.w", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x750f8000, 0xffff8000, "xvbitset.d", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x75100000, 0xffff8000, "xvbitrev.b", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x75108000, 0xffff8000, "xvbitrev.h", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x75110000, 0xffff8000, "xvbitrev.w", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x75118000, 0xffff8000, "xvbitrev.d", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x75160000, 0xffff8000, "xvpackev.b", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x75168000, 0xffff8000, "xvpackev.h", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x75170000, 0xffff8000, "xvpackev.w", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x75178000, 0xffff8000, "xvpackev.d", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x75180000, 0xffff8000, "xvpackod.b", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x75188000, 0xffff8000, "xvpackod.h", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x75190000, 0xffff8000, "xvpackod.w", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x75198000, 0xffff8000, "xvpackod.d", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x751a0000, 0xffff8000, "xvilvl.b", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x751a8000, 0xffff8000, "xvilvl.h", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x751b0000, 0xffff8000, "xvilvl.w", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x751b8000, 0xffff8000, "xvilvl.d", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x751c0000, 0xffff8000, "xvilvh.b", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x751c8000, 0xffff8000, "xvilvh.h", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x751d0000, 0xffff8000, "xvilvh.w", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x751d8000, 0xffff8000, "xvilvh.d", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x751e0000, 0xffff8000, "xvpickev.b", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x751e8000, 0xffff8000, "xvpickev.h", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x751f0000, 0xffff8000, "xvpickev.w", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x751f8000, 0xffff8000, "xvpickev.d", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x75200000, 0xffff8000, "xvpickod.b", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x75208000, 0xffff8000, "xvpickod.h", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x75210000, 0xffff8000, "xvpickod.w", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x75218000, 0xffff8000, "xvpickod.d", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x75220000, 0xffff8000, "xvreplve.b", "x0:5,x5:5,r10:5", 0, 0, 0, 0}, + { 0x75228000, 0xffff8000, "xvreplve.h", "x0:5,x5:5,r10:5", 0, 0, 0, 0}, + { 0x75230000, 0xffff8000, "xvreplve.w", "x0:5,x5:5,r10:5", 0, 0, 0, 0}, + { 0x75238000, 0xffff8000, "xvreplve.d", "x0:5,x5:5,r10:5", 0, 0, 0, 0}, + { 0x75260000, 0xffff8000, "xvand.v", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x75268000, 0xffff8000, "xvor.v", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x75270000, 0xffff8000, "xvxor.v", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x75278000, 0xffff8000, "xvnor.v", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x75280000, 0xffff8000, "xvandn.v", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x75288000, 0xffff8000, "xvorn.v", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x752b0000, 0xffff8000, "xvfrstp.b", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x752b8000, 0xffff8000, "xvfrstp.h", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x752d0000, 0xffff8000, "xvadd.q", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x752d8000, 0xffff8000, "xvsub.q", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x752e0000, 0xffff8000, "xvsigncov.b", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x752e8000, 0xffff8000, "xvsigncov.h", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x752f0000, 0xffff8000, "xvsigncov.w", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x752f8000, 0xffff8000, "xvsigncov.d", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x75308000, 0xffff8000, "xvfadd.s", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x75310000, 0xffff8000, "xvfadd.d", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x75328000, 0xffff8000, "xvfsub.s", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x75330000, 0xffff8000, "xvfsub.d", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x75388000, 0xffff8000, "xvfmul.s", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x75390000, 0xffff8000, "xvfmul.d", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x753a8000, 0xffff8000, "xvfdiv.s", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x753b0000, 0xffff8000, "xvfdiv.d", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x753c8000, 0xffff8000, "xvfmax.s", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x753d0000, 0xffff8000, "xvfmax.d", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x753e8000, 0xffff8000, "xvfmin.s", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x753f0000, 0xffff8000, "xvfmin.d", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x75408000, 0xffff8000, "xvfmaxa.s", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x75410000, 0xffff8000, "xvfmaxa.d", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x75428000, 0xffff8000, "xvfmina.s", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x75430000, 0xffff8000, "xvfmina.d", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x75460000, 0xffff8000, "xvfcvt.h.s", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x75468000, 0xffff8000, "xvfcvt.s.d", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x75480000, 0xffff8000, "xvffint.s.l", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x75498000, 0xffff8000, "xvftint.w.d", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x754a0000, 0xffff8000, "xvftintrm.w.d", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x754a8000, 0xffff8000, "xvftintrp.w.d", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x754b0000, 0xffff8000, "xvftintrz.w.d", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x754b8000, 0xffff8000, "xvftintrne.w.d", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x757a8000, 0xffff8000, "xvshuf.h", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x757b0000, 0xffff8000, "xvshuf.w", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x757b8000, 0xffff8000, "xvshuf.d", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x757d0000, 0xffff8000, "xvperm.w", "x0:5,x5:5,x10:5", 0, 0, 0, 0 }, + { 0x76800000, 0xffff8000, "xvseqi.b", "x0:5,x5:5,s10:5", 0, 0, 0, 0}, + { 0x76808000, 0xffff8000, "xvseqi.h", "x0:5,x5:5,s10:5", 0, 0, 0, 0}, + { 0x76810000, 0xffff8000, "xvseqi.w", "x0:5,x5:5,s10:5", 0, 0, 0, 0}, + { 0x76818000, 0xffff8000, "xvseqi.d", "x0:5,x5:5,s10:5", 0, 0, 0, 0}, + { 0x76820000, 0xffff8000, "xvslei.b", "x0:5,x5:5,s10:5", 0, 0, 0, 0}, + { 0x76828000, 0xffff8000, "xvslei.h", "x0:5,x5:5,s10:5", 0, 0, 0, 0}, + { 0x76830000, 0xffff8000, "xvslei.w", "x0:5,x5:5,s10:5", 0, 0, 0, 0}, + { 0x76838000, 0xffff8000, "xvslei.d", "x0:5,x5:5,s10:5", 0, 0, 0, 0}, + { 0x76840000, 0xffff8000, "xvslei.bu", "x0:5,x5:5,u10:5", 0, 0, 0, 0}, + { 0x76848000, 0xffff8000, "xvslei.hu", "x0:5,x5:5,u10:5", 0, 0, 0, 0}, + { 0x76850000, 0xffff8000, "xvslei.wu", "x0:5,x5:5,u10:5", 0, 0, 0, 0}, + { 0x76858000, 0xffff8000, "xvslei.du", "x0:5,x5:5,u10:5", 0, 0, 0, 0}, + { 0x76860000, 0xffff8000, "xvslti.b", "x0:5,x5:5,s10:5", 0, 0, 0, 0}, + { 0x76868000, 0xffff8000, "xvslti.h", "x0:5,x5:5,s10:5", 0, 0, 0, 0}, + { 0x76870000, 0xffff8000, "xvslti.w", "x0:5,x5:5,s10:5", 0, 0, 0, 0}, + { 0x76878000, 0xffff8000, "xvslti.d", "x0:5,x5:5,s10:5", 0, 0, 0, 0}, + { 0x76880000, 0xffff8000, "xvslti.bu", "x0:5,x5:5,u10:5", 0, 0, 0, 0}, + { 0x76888000, 0xffff8000, "xvslti.hu", "x0:5,x5:5,u10:5", 0, 0, 0, 0}, + { 0x76890000, 0xffff8000, "xvslti.wu", "x0:5,x5:5,u10:5", 0, 0, 0, 0}, + { 0x76898000, 0xffff8000, "xvslti.du", "x0:5,x5:5,u10:5", 0, 0, 0, 0}, + { 0x768a0000, 0xffff8000, "xvaddi.bu", "x0:5,x5:5,u10:5", 0, 0, 0, 0}, + { 0x768a8000, 0xffff8000, "xvaddi.hu", "x0:5,x5:5,u10:5", 0, 0, 0, 0}, + { 0x768b0000, 0xffff8000, "xvaddi.wu", "x0:5,x5:5,u10:5", 0, 0, 0, 0}, + { 0x768b8000, 0xffff8000, "xvaddi.du", "x0:5,x5:5,u10:5", 0, 0, 0, 0}, + { 0x768c0000, 0xffff8000, "xvsubi.bu", "x0:5,x5:5,u10:5", 0, 0, 0, 0}, + { 0x768c8000, 0xffff8000, "xvsubi.hu", "x0:5,x5:5,u10:5", 0, 0, 0, 0}, + { 0x768d0000, 0xffff8000, "xvsubi.wu", "x0:5,x5:5,u10:5", 0, 0, 0, 0}, + { 0x768d8000, 0xffff8000, "xvsubi.du", "x0:5,x5:5,u10:5", 0, 0, 0, 0}, + { 0x768e0000, 0xffff8000, "xvbsll.v", "x0:5,x5:5,u10:5", 0, 0, 0, 0}, + { 0x768e8000, 0xffff8000, "xvbsrl.v", "x0:5,x5:5,u10:5", 0, 0, 0, 0}, + { 0x76900000, 0xffff8000, "xvmaxi.b", "x0:5,x5:5,s10:5", 0, 0, 0, 0}, + { 0x76908000, 0xffff8000, "xvmaxi.h", "x0:5,x5:5,s10:5", 0, 0, 0, 0}, + { 0x76910000, 0xffff8000, "xvmaxi.w", "x0:5,x5:5,s10:5", 0, 0, 0, 0}, + { 0x76918000, 0xffff8000, "xvmaxi.d", "x0:5,x5:5,s10:5", 0, 0, 0, 0}, + { 0x76920000, 0xffff8000, "xvmini.b", "x0:5,x5:5,s10:5", 0, 0, 0, 0}, + { 0x76928000, 0xffff8000, "xvmini.h", "x0:5,x5:5,s10:5", 0, 0, 0, 0}, + { 0x76930000, 0xffff8000, "xvmini.w", "x0:5,x5:5,s10:5", 0, 0, 0, 0}, + { 0x76938000, 0xffff8000, "xvmini.d", "x0:5,x5:5,s10:5", 0, 0, 0, 0}, + { 0x76940000, 0xffff8000, "xvmaxi.bu", "x0:5,x5:5,u10:5", 0, 0, 0, 0}, + { 0x76948000, 0xffff8000, "xvmaxi.hu", "x0:5,x5:5,u10:5", 0, 0, 0, 0}, + { 0x76950000, 0xffff8000, "xvmaxi.wu", "x0:5,x5:5,u10:5", 0, 0, 0, 0}, + { 0x76958000, 0xffff8000, "xvmaxi.du", "x0:5,x5:5,u10:5", 0, 0, 0, 0}, + { 0x76960000, 0xffff8000, "xvmini.bu", "x0:5,x5:5,u10:5", 0, 0, 0, 0}, + { 0x76968000, 0xffff8000, "xvmini.hu", "x0:5,x5:5,u10:5", 0, 0, 0, 0}, + { 0x76970000, 0xffff8000, "xvmini.wu", "x0:5,x5:5,u10:5", 0, 0, 0, 0}, + { 0x76978000, 0xffff8000, "xvmini.du", "x0:5,x5:5,u10:5", 0, 0, 0, 0}, + { 0x769a0000, 0xffff8000, "xvfrstpi.b", "x0:5,x5:5,u10:5", 0, 0, 0, 0}, + { 0x769a8000, 0xffff8000, "xvfrstpi.h", "x0:5,x5:5,u10:5", 0, 0, 0, 0}, + { 0x769c0000, 0xfffffc00, "xvclo.b", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769c0400, 0xfffffc00, "xvclo.h", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769c0800, 0xfffffc00, "xvclo.w", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769c0c00, 0xfffffc00, "xvclo.d", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769c1000, 0xfffffc00, "xvclz.b", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769c1400, 0xfffffc00, "xvclz.h", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769c1800, 0xfffffc00, "xvclz.w", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769c1c00, 0xfffffc00, "xvclz.d", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769c2000, 0xfffffc00, "xvpcnt.b", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769c2400, 0xfffffc00, "xvpcnt.h", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769c2800, 0xfffffc00, "xvpcnt.w", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769c2c00, 0xfffffc00, "xvpcnt.d", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769c3000, 0xfffffc00, "xvneg.b", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769c3400, 0xfffffc00, "xvneg.h", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769c3800, 0xfffffc00, "xvneg.w", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769c3c00, 0xfffffc00, "xvneg.d", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769c4000, 0xfffffc00, "xvmskltz.b", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769c4400, 0xfffffc00, "xvmskltz.h", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769c4800, 0xfffffc00, "xvmskltz.w", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769c4c00, 0xfffffc00, "xvmskltz.d", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769c5000, 0xfffffc00, "xvmskgez.b", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769c6000, 0xfffffc00, "xvmsknz.b", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769c9800, 0xfffffc18, "xvseteqz.v", "c0:3,x5:5", 0, 0, 0, 0}, + { 0x769c9c00, 0xfffffc18, "xvsetnez.v", "c0:3,x5:5", 0, 0, 0, 0}, + { 0x769ca000, 0xfffffc18, "xvsetanyeqz.b", "c0:3,x5:5", 0, 0, 0, 0}, + { 0x769ca400, 0xfffffc18, "xvsetanyeqz.h", "c0:3,x5:5", 0, 0, 0, 0}, + { 0x769ca800, 0xfffffc18, "xvsetanyeqz.w", "c0:3,x5:5", 0, 0, 0, 0}, + { 0x769cac00, 0xfffffc18, "xvsetanyeqz.d", "c0:3,x5:5", 0, 0, 0, 0}, + { 0x769cb000, 0xfffffc18, "xvsetallnez.b", "c0:3,x5:5", 0, 0, 0, 0}, + { 0x769cb400, 0xfffffc18, "xvsetallnez.h", "c0:3,x5:5", 0, 0, 0, 0}, + { 0x769cb800, 0xfffffc18, "xvsetallnez.w", "c0:3,x5:5", 0, 0, 0, 0}, + { 0x769cbc00, 0xfffffc18, "xvsetallnez.d", "c0:3,x5:5", 0, 0, 0, 0}, + { 0x769cc400, 0xfffffc00, "xvflogb.s", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769cc800, 0xfffffc00, "xvflogb.d", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769cd400, 0xfffffc00, "xvfclass.s", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769cd800, 0xfffffc00, "xvfclass.d", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769ce400, 0xfffffc00, "xvfsqrt.s", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769ce800, 0xfffffc00, "xvfsqrt.d", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769cf400, 0xfffffc00, "xvfrecip.s", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769cf800, 0xfffffc00, "xvfrecip.d", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769d0400, 0xfffffc00, "xvfrsqrt.s", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769d0800, 0xfffffc00, "xvfrsqrt.d", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769d3400, 0xfffffc00, "xvfrint.s", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769d3800, 0xfffffc00, "xvfrint.d", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769d4400, 0xfffffc00, "xvfrintrm.s", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769d4800, 0xfffffc00, "xvfrintrm.d", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769d5400, 0xfffffc00, "xvfrintrp.s", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769d5800, 0xfffffc00, "xvfrintrp.d", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769d6400, 0xfffffc00, "xvfrintrz.s", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769d6800, 0xfffffc00, "xvfrintrz.d", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769d7400, 0xfffffc00, "xvfrintrne.s", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769d7800, 0xfffffc00, "xvfrintrne.d", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769de800, 0xfffffc00, "xvfcvtl.s.h", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769dec00, 0xfffffc00, "xvfcvth.s.h", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769df000, 0xfffffc00, "xvfcvtl.d.s", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769df400, 0xfffffc00, "xvfcvth.d.s", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769e0000, 0xfffffc00, "xvffint.s.w", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769e0400, 0xfffffc00, "xvffint.s.wu", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769e0800, 0xfffffc00, "xvffint.d.l", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769e0c00, 0xfffffc00, "xvffint.d.lu", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769e1000, 0xfffffc00, "xvffintl.d.w", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769e1400, 0xfffffc00, "xvffinth.d.w", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769e3000, 0xfffffc00, "xvftint.w.s", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769e3400, 0xfffffc00, "xvftint.l.d", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769e3800, 0xfffffc00, "xvftintrm.w.s", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769e3c00, 0xfffffc00, "xvftintrm.l.d", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769e4000, 0xfffffc00, "xvftintrp.w.s", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769e4400, 0xfffffc00, "xvftintrp.l.d", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769e4800, 0xfffffc00, "xvftintrz.w.s", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769e4c00, 0xfffffc00, "xvftintrz.l.d", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769e5000, 0xfffffc00, "xvftintrne.w.s", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769e5400, 0xfffffc00, "xvftintrne.l.d", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769e5800, 0xfffffc00, "xvftint.wu.s", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769e5c00, 0xfffffc00, "xvftint.lu.d", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769e7000, 0xfffffc00, "xvftintrz.wu.s", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769e7400, 0xfffffc00, "xvftintrz.lu.d", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769e8000, 0xfffffc00, "xvftintl.l.s", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769e8400, 0xfffffc00, "xvftinth.l.s", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769e8800, 0xfffffc00, "xvftintrml.l.s", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769e8c00, 0xfffffc00, "xvftintrmh.l.s", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769e9000, 0xfffffc00, "xvftintrpl.l.s", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769e9400, 0xfffffc00, "xvftintrph.l.s", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769e9800, 0xfffffc00, "xvftintrzl.l.s", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769e9c00, 0xfffffc00, "xvftintrzh.l.s", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769ea000, 0xfffffc00, "xvftintrnel.l.s", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769ea400, 0xfffffc00, "xvftintrneh.l.s", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769ee000, 0xfffffc00, "xvexth.h.b", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769ee400, 0xfffffc00, "xvexth.w.h", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769ee800, 0xfffffc00, "xvexth.d.w", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769eec00, 0xfffffc00, "xvexth.q.d", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769ef000, 0xfffffc00, "xvexth.hu.bu", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769ef400, 0xfffffc00, "xvexth.wu.hu", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769ef800, 0xfffffc00, "xvexth.du.wu", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769efc00, 0xfffffc00, "xvexth.qu.du", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769f0000, 0xfffffc00, "xvreplgr2vr.b", "x0:5,r5:5", 0, 0, 0, 0}, + { 0x769f0400, 0xfffffc00, "xvreplgr2vr.h", "x0:5,r5:5", 0, 0, 0, 0}, + { 0x769f0800, 0xfffffc00, "xvreplgr2vr.w", "x0:5,r5:5", 0, 0, 0, 0}, + { 0x769f0c00, 0xfffffc00, "xvreplgr2vr.d", "x0:5,r5:5", 0, 0, 0, 0}, + { 0x769f1000, 0xfffffc00, "vext2xv.h.b", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769f1400, 0xfffffc00, "vext2xv.w.b", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769f1800, 0xfffffc00, "vext2xv.d.b", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769f1c00, 0xfffffc00, "vext2xv.w.h", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769f2000, 0xfffffc00, "vext2xv.d.h", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769f2400, 0xfffffc00, "vext2xv.d.w", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769f2800, 0xfffffc00, "vext2xv.hu.bu", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769f2c00, 0xfffffc00, "vext2xv.wu.bu", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769f3000, 0xfffffc00, "vext2xv.du.bu", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769f3400, 0xfffffc00, "vext2xv.wu.hu", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769f3800, 0xfffffc00, "vext2xv.du.hu", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769f3c00, 0xfffffc00, "vext2xv.du.wu", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769f8000, 0xffff8000, "xvhseli.d", "x0:5,x5:5,u10:5", 0, 0, 0, 0}, + { 0x76a02000, 0xffffe000, "xvrotri.b", "x0:5,x5:5,u10:3", 0, 0, 0, 0}, + { 0x76a04000, 0xffffc000, "xvrotri.h", "x0:5,x5:5,u10:4", 0, 0, 0, 0}, + { 0x76a08000, 0xffff8000, "xvrotri.w", "x0:5,x5:5,u10:5", 0, 0, 0, 0}, + { 0x76a10000, 0xffff0000, "xvrotri.d", "x0:5,x5:5,u10:6", 0, 0, 0, 0}, + { 0x76a42000, 0xffffe000, "xvsrlri.b", "x0:5,x5:5,u10:3", 0, 0, 0, 0}, + { 0x76a44000, 0xffffc000, "xvsrlri.h", "x0:5,x5:5,u10:4", 0, 0, 0, 0}, + { 0x76a48000, 0xffff8000, "xvsrlri.w", "x0:5,x5:5,u10:5", 0, 0, 0, 0}, + { 0x76a50000, 0xffff0000, "xvsrlri.d", "x0:5,x5:5,u10:6", 0, 0, 0, 0}, + { 0x76a82000, 0xffffe000, "xvsrari.b", "x0:5,x5:5,u10:3", 0, 0, 0, 0}, + { 0x76a84000, 0xffffc000, "xvsrari.h", "x0:5,x5:5,u10:4", 0, 0, 0, 0}, + { 0x76a88000, 0xffff8000, "xvsrari.w", "x0:5,x5:5,u10:5", 0, 0, 0, 0}, + { 0x76a90000, 0xffff0000, "xvsrari.d", "x0:5,x5:5,u10:6", 0, 0, 0, 0}, + { 0x76ebc000, 0xffffe000, "xvinsgr2vr.w", "x0:5,r5:5,u10:3", 0, 0, 0, 0}, + { 0x76ebe000, 0xfffff000, "xvinsgr2vr.d", "x0:5,r5:5,u10:2", 0, 0, 0, 0}, + { 0x76efc000, 0xffffe000, "xvpickve2gr.w", "r0:5,x5:5,u10:3", 0, 0, 0, 0}, + { 0x76efe000, 0xfffff000, "xvpickve2gr.d", "r0:5,x5:5,u10:2", 0, 0, 0, 0}, + { 0x76f3c000, 0xffffe000, "xvpickve2gr.wu", "r0:5,x5:5,u10:3", 0, 0, 0, 0}, + { 0x76f3e000, 0xfffff000, "xvpickve2gr.du", "r0:5,x5:5,u10:2", 0, 0, 0, 0}, + { 0x76f78000, 0xffffc000, "xvrepl128vei.b", "x0:5,x5:5,u10:4", 0, 0, 0, 0}, + { 0x76f7c000, 0xffffe000, "xvrepl128vei.h", "x0:5,x5:5,u10:3", 0, 0, 0, 0}, + { 0x76f7e000, 0xfffff000, "xvrepl128vei.w", "x0:5,x5:5,u10:2", 0, 0, 0, 0}, + { 0x76f7f000, 0xfffff800, "xvrepl128vei.d", "x0:5,x5:5,u10:1", 0, 0, 0, 0}, + { 0x76ffc000, 0xffffe000, "xvinsve0.w", "x0:5,x5:5,u10:3", 0, 0, 0, 0}, + { 0x76ffe000, 0xfffff000, "xvinsve0.d", "x0:5,x5:5,u10:2", 0, 0, 0, 0}, + { 0x7703c000, 0xffffe000, "xvpickve.w", "x0:5,x5:5,u10:3", 0, 0, 0, 0}, + { 0x7703e000, 0xfffff000, "xvpickve.d", "x0:5,x5:5,u10:2", 0, 0, 0, 0}, + { 0x77070000, 0xfffffc00, "xvreplve0.b", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x77078000, 0xfffffc00, "xvreplve0.h", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x7707c000, 0xfffffc00, "xvreplve0.w", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x7707e000, 0xfffffc00, "xvreplve0.d", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x7707f000, 0xfffffc00, "xvreplve0.q", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x77082000, 0xffffe000, "xvsllwil.h.b", "x0:5,x5:5,u10:3", 0, 0, 0, 0}, + { 0x77084000, 0xffffc000, "xvsllwil.w.h", "x0:5,x5:5,u10:4", 0, 0, 0, 0}, + { 0x77088000, 0xffff8000, "xvsllwil.d.w", "x0:5,x5:5,u10:5", 0, 0, 0, 0}, + { 0x77090000, 0xfffffc00, "xvextl.q.d", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x770c2000, 0xffffe000, "xvsllwil.hu.bu", "x0:5,x5:5,u10:3", 0, 0, 0, 0}, + { 0x770c4000, 0xffffc000, "xvsllwil.wu.hu", "x0:5,x5:5,u10:4", 0, 0, 0, 0}, + { 0x770c8000, 0xffff8000, "xvsllwil.du.wu", "x0:5,x5:5,u10:5", 0, 0, 0, 0}, + { 0x770d0000, 0xfffffc00, "xvextl.qu.du", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x77102000, 0xffffe000, "xvbitclri.b", "x0:5,x5:5,u10:3", 0, 0, 0, 0}, + { 0x77104000, 0xffffc000, "xvbitclri.h", "x0:5,x5:5,u10:4", 0, 0, 0, 0}, + { 0x77108000, 0xffff8000, "xvbitclri.w", "x0:5,x5:5,u10:5", 0, 0, 0, 0}, + { 0x77110000, 0xffff0000, "xvbitclri.d", "x0:5,x5:5,u10:6", 0, 0, 0, 0}, + { 0x77142000, 0xffffe000, "xvbitseti.b", "x0:5,x5:5,u10:3", 0, 0, 0, 0}, + { 0x77144000, 0xffffc000, "xvbitseti.h", "x0:5,x5:5,u10:4", 0, 0, 0, 0}, + { 0x77148000, 0xffff8000, "xvbitseti.w", "x0:5,x5:5,u10:5", 0, 0, 0, 0}, + { 0x77150000, 0xffff0000, "xvbitseti.d", "x0:5,x5:5,u10:6", 0, 0, 0, 0}, + { 0x77182000, 0xffffe000, "xvbitrevi.b", "x0:5,x5:5,u10:3", 0, 0, 0, 0}, + { 0x77184000, 0xffffc000, "xvbitrevi.h", "x0:5,x5:5,u10:4", 0, 0, 0, 0}, + { 0x77188000, 0xffff8000, "xvbitrevi.w", "x0:5,x5:5,u10:5", 0, 0, 0, 0}, + { 0x77190000, 0xffff0000, "xvbitrevi.d", "x0:5,x5:5,u10:6", 0, 0, 0, 0}, + { 0x77242000, 0xffffe000, "xvsat.b", "x0:5,x5:5,u10:3", 0, 0, 0, 0}, + { 0x77244000, 0xffffc000, "xvsat.h", "x0:5,x5:5,u10:4", 0, 0, 0, 0}, + { 0x77248000, 0xffff8000, "xvsat.w", "x0:5,x5:5,u10:5", 0, 0, 0, 0}, + { 0x77250000, 0xffff0000, "xvsat.d", "x0:5,x5:5,u10:6", 0, 0, 0, 0}, + { 0x77282000, 0xffffe000, "xvsat.bu", "x0:5,x5:5,u10:3", 0, 0, 0, 0}, + { 0x77284000, 0xffffc000, "xvsat.hu", "x0:5,x5:5,u10:4", 0, 0, 0, 0}, + { 0x77288000, 0xffff8000, "xvsat.wu", "x0:5,x5:5,u10:5", 0, 0, 0, 0}, + { 0x77290000, 0xffff0000, "xvsat.du", "x0:5,x5:5,u10:6", 0, 0, 0, 0}, + { 0x772c2000, 0xffffe000, "xvslli.b", "x0:5,x5:5,u10:3", 0, 0, 0, 0}, + { 0x772c4000, 0xffffc000, "xvslli.h", "x0:5,x5:5,u10:4", 0, 0, 0, 0}, + { 0x772c8000, 0xffff8000, "xvslli.w", "x0:5,x5:5,u10:5", 0, 0, 0, 0}, + { 0x772d0000, 0xffff0000, "xvslli.d", "x0:5,x5:5,u10:6", 0, 0, 0, 0}, + { 0x77302000, 0xffffe000, "xvsrli.b", "x0:5,x5:5,u10:3", 0, 0, 0, 0}, + { 0x77304000, 0xffffc000, "xvsrli.h", "x0:5,x5:5,u10:4", 0, 0, 0, 0}, + { 0x77308000, 0xffff8000, "xvsrli.w", "x0:5,x5:5,u10:5", 0, 0, 0, 0}, + { 0x77310000, 0xffff0000, "xvsrli.d", "x0:5,x5:5,u10:6", 0, 0, 0, 0}, + { 0x77342000, 0xffffe000, "xvsrai.b", "x0:5,x5:5,u10:3", 0, 0, 0, 0}, + { 0x77344000, 0xffffc000, "xvsrai.h", "x0:5,x5:5,u10:4", 0, 0, 0, 0}, + { 0x77348000, 0xffff8000, "xvsrai.w", "x0:5,x5:5,u10:5", 0, 0, 0, 0}, + { 0x77350000, 0xffff0000, "xvsrai.d", "x0:5,x5:5,u10:6", 0, 0, 0, 0}, + { 0x77404000, 0xffffc000, "xvsrlni.b.h", "x0:5,x5:5,u10:4", 0, 0, 0, 0}, + { 0x77408000, 0xffff8000, "xvsrlni.h.w", "x0:5,x5:5,u10:5", 0, 0, 0, 0}, + { 0x77410000, 0xffff0000, "xvsrlni.w.d", "x0:5,x5:5,u10:6", 0, 0, 0, 0}, + { 0x77420000, 0xfffe0000, "xvsrlni.d.q", "x0:5,x5:5,u10:7", 0, 0, 0, 0}, + { 0x77444000, 0xffffc000, "xvsrlrni.b.h", "x0:5,x5:5,u10:4", 0, 0, 0, 0}, + { 0x77448000, 0xffff8000, "xvsrlrni.h.w", "x0:5,x5:5,u10:5", 0, 0, 0, 0}, + { 0x77450000, 0xffff0000, "xvsrlrni.w.d", "x0:5,x5:5,u10:6", 0, 0, 0, 0}, + { 0x77460000, 0xfffe0000, "xvsrlrni.d.q", "x0:5,x5:5,u10:7", 0, 0, 0, 0}, + { 0x77484000, 0xffffc000, "xvssrlni.b.h", "x0:5,x5:5,u10:4", 0, 0, 0, 0}, + { 0x77488000, 0xffff8000, "xvssrlni.h.w", "x0:5,x5:5,u10:5", 0, 0, 0, 0}, + { 0x77490000, 0xffff0000, "xvssrlni.w.d", "x0:5,x5:5,u10:6", 0, 0, 0, 0}, + { 0x774a0000, 0xfffe0000, "xvssrlni.d.q", "x0:5,x5:5,u10:7", 0, 0, 0, 0}, + { 0x774c4000, 0xffffc000, "xvssrlni.bu.h", "x0:5,x5:5,u10:4", 0, 0, 0, 0}, + { 0x774c8000, 0xffff8000, "xvssrlni.hu.w", "x0:5,x5:5,u10:5", 0, 0, 0, 0}, + { 0x774d0000, 0xffff0000, "xvssrlni.wu.d", "x0:5,x5:5,u10:6", 0, 0, 0, 0}, + { 0x774e0000, 0xfffe0000, "xvssrlni.du.q", "x0:5,x5:5,u10:7", 0, 0, 0, 0}, + { 0x77504000, 0xffffc000, "xvssrlrni.b.h", "x0:5,x5:5,u10:4", 0, 0, 0, 0}, + { 0x77508000, 0xffff8000, "xvssrlrni.h.w", "x0:5,x5:5,u10:5", 0, 0, 0, 0}, + { 0x77510000, 0xffff0000, "xvssrlrni.w.d", "x0:5,x5:5,u10:6", 0, 0, 0, 0}, + { 0x77520000, 0xfffe0000, "xvssrlrni.d.q", "x0:5,x5:5,u10:7", 0, 0, 0, 0}, + { 0x77544000, 0xffffc000, "xvssrlrni.bu.h", "x0:5,x5:5,u10:4", 0, 0, 0, 0}, + { 0x77548000, 0xffff8000, "xvssrlrni.hu.w", "x0:5,x5:5,u10:5", 0, 0, 0, 0}, + { 0x77550000, 0xffff0000, "xvssrlrni.wu.d", "x0:5,x5:5,u10:6", 0, 0, 0, 0}, + { 0x77560000, 0xfffe0000, "xvssrlrni.du.q", "x0:5,x5:5,u10:7", 0, 0, 0, 0}, + { 0x77584000, 0xffffc000, "xvsrani.b.h", "x0:5,x5:5,u10:4", 0, 0, 0, 0}, + { 0x77588000, 0xffff8000, "xvsrani.h.w", "x0:5,x5:5,u10:5", 0, 0, 0, 0}, + { 0x77590000, 0xffff0000, "xvsrani.w.d", "x0:5,x5:5,u10:6", 0, 0, 0, 0}, + { 0x775a0000, 0xfffe0000, "xvsrani.d.q", "x0:5,x5:5,u10:7", 0, 0, 0, 0}, + { 0x775c4000, 0xffffc000, "xvsrarni.b.h", "x0:5,x5:5,u10:4", 0, 0, 0, 0}, + { 0x775c8000, 0xffff8000, "xvsrarni.h.w", "x0:5,x5:5,u10:5", 0, 0, 0, 0}, + { 0x775d0000, 0xffff0000, "xvsrarni.w.d", "x0:5,x5:5,u10:6", 0, 0, 0, 0}, + { 0x775e0000, 0xfffe0000, "xvsrarni.d.q", "x0:5,x5:5,u10:7", 0, 0, 0, 0}, + { 0x77604000, 0xffffc000, "xvssrani.b.h", "x0:5,x5:5,u10:4", 0, 0, 0, 0}, + { 0x77608000, 0xffff8000, "xvssrani.h.w", "x0:5,x5:5,u10:5", 0, 0, 0, 0}, + { 0x77610000, 0xffff0000, "xvssrani.w.d", "x0:5,x5:5,u10:6", 0, 0, 0, 0}, + { 0x77620000, 0xfffe0000, "xvssrani.d.q", "x0:5,x5:5,u10:7", 0, 0, 0, 0}, + { 0x77644000, 0xffffc000, "xvssrani.bu.h", "x0:5,x5:5,u10:4", 0, 0, 0, 0}, + { 0x77648000, 0xffff8000, "xvssrani.hu.w", "x0:5,x5:5,u10:5", 0, 0, 0, 0}, + { 0x77650000, 0xffff0000, "xvssrani.wu.d", "x0:5,x5:5,u10:6", 0, 0, 0, 0}, + { 0x77660000, 0xfffe0000, "xvssrani.du.q", "x0:5,x5:5,u10:7", 0, 0, 0, 0}, + { 0x77684000, 0xffffc000, "xvssrarni.b.h", "x0:5,x5:5,u10:4", 0, 0, 0, 0}, + { 0x77688000, 0xffff8000, "xvssrarni.h.w", "x0:5,x5:5,u10:5", 0, 0, 0, 0}, + { 0x77690000, 0xffff0000, "xvssrarni.w.d", "x0:5,x5:5,u10:6", 0, 0, 0, 0}, + { 0x776a0000, 0xfffe0000, "xvssrarni.d.q", "x0:5,x5:5,u10:7", 0, 0, 0, 0}, + { 0x776c4000, 0xffffc000, "xvssrarni.bu.h", "x0:5,x5:5,u10:4", 0, 0, 0, 0}, + { 0x776c8000, 0xffff8000, "xvssrarni.hu.w", "x0:5,x5:5,u10:5", 0, 0, 0, 0}, + { 0x776d0000, 0xffff0000, "xvssrarni.wu.d", "x0:5,x5:5,u10:6", 0, 0, 0, 0}, + { 0x776e0000, 0xfffe0000, "xvssrarni.du.q", "x0:5,x5:5,u10:7", 0, 0, 0, 0}, + { 0x77800000, 0xfffc0000, "xvextrins.d", "x0:5,x5:5,u10:8", 0, 0, 0, 0}, + { 0x77840000, 0xfffc0000, "xvextrins.w", "x0:5,x5:5,u10:8", 0, 0, 0, 0}, + { 0x77880000, 0xfffc0000, "xvextrins.h", "x0:5,x5:5,u10:8", 0, 0, 0, 0}, + { 0x778c0000, 0xfffc0000, "xvextrins.b", "x0:5,x5:5,u10:8", 0, 0, 0, 0}, + { 0x77900000, 0xfffc0000, "xvshuf4i.b", "x0:5,x5:5,u10:8", 0, 0, 0, 0}, + { 0x77940000, 0xfffc0000, "xvshuf4i.h", "x0:5,x5:5,u10:8", 0, 0, 0, 0}, + { 0x77980000, 0xfffc0000, "xvshuf4i.w", "x0:5,x5:5,u10:8", 0, 0, 0, 0}, + { 0x779c0000, 0xfffc0000, "xvshuf4i.d", "x0:5,x5:5,u10:8", 0, 0, 0, 0}, + { 0x77c40000, 0xfffc0000, "xvbitseli.b", "x0:5,x5:5,u10:8", 0, 0, 0, 0}, + { 0x77d00000, 0xfffc0000, "xvandi.b", "x0:5,x5:5,u10:8", 0, 0, 0, 0}, + { 0x77d40000, 0xfffc0000, "xvori.b", "x0:5,x5:5,u10:8", 0, 0, 0, 0}, + { 0x77d80000, 0xfffc0000, "xvxori.b", "x0:5,x5:5,u10:8", 0, 0, 0, 0}, + { 0x77dc0000, 0xfffc0000, "xvnori.b", "x0:5,x5:5,u10:8", 0, 0, 0, 0}, + { 0, 0, "xvrepli.b", "x,s0:10", "xvldi %1,(%2)&0x3ff", 0, 0, 0}, + { 0, 0, "xvrepli.d", "x,s0:10", "xvldi %1,((%2)&0x3ff)|0xc00", 0, 0, 0}, + { 0, 0, "xvrepli.h", "x,s0:10", "xvldi %1,((%2)&0x3ff)|0x400", 0, 0, 0}, + { 0, 0, "xvrepli.w", "x,s0:10", "xvldi %1,((%2)&0x3ff)|0x800", 0, 0, 0}, + { 0x77e00000, 0xfffc0000, "xvldi", "x0:5,s5:13", 0, 0, 0, 0}, + { 0x77e40000, 0xfffc0000, "xvpermi.w", "x0:5,x5:5,u10:8", 0, 0, 0, 0}, + { 0x77e80000, 0xfffc0000, "xvpermi.d", "x0:5,x5:5,u10:8", 0, 0, 0, 0}, + { 0x77ec0000, 0xfffc0000, "xvpermi.q", "x0:5,x5:5,u10:8", 0, 0, 0, 0}, + { 0, 0, 0, 0, 0, 0, 0, 0 } /* Terminate the list. */ +}; + +static struct loongarch_opcode loongarch_lvz_opcodes[] = +{ + /* match, mask, name, format, macro, include, exclude, pinfo. */ + {0x05000000, 0xff0003e0, "gcsrrd", "r0:5,u10:14", 0, 0, 0, 0}, + {0x05000020, 0xff0003e0, "gcsrwr", "r0:5,u10:14", 0, 0, 0, 0}, + {0x05000000, 0xff000000, "gcsrxchg", "r0:5,r5:5,u10:14", 0, 0, 0, 0}, + {0x06482401, 0xffffffff, "gtlbflush", "", 0, 0, 0, 0}, + {0x002b8000, 0xffff8000, "hvcl", "u0:15", 0, 0, 0, 0}, + { 0, 0, 0, 0, 0, 0, 0, 0 } /* Terminate the list. */ +}; + +static struct loongarch_opcode loongarch_lbt_opcodes[] = +{ + /* match, mask, name, format, macro, include, exclude, pinfo. */ + {0x00000800, 0xfffffc1c, "movgr2scr", "cr0:2,r5:5", 0, 0, 0, 0}, + {0x00000c00, 0xffffff80, "movscr2gr", "r0:5,cr5:2", 0, 0, 0, 0}, + {0x48000200, 0xfc0003e0, "jiscr0", "s0:5|10:16<<2", 0, 0, 0, 0}, + {0x48000300, 0xfc0003e0, "jiscr1", "s0:5|10:16<<2", 0, 0, 0, 0}, + {0x00290000, 0xffff8000, "addu12i.w", "r0:5,r5:5,s10:5", 0, 0, 0, 0}, + {0x00298000, 0xffff8000, "addu12i.d", "r0:5,r5:5,s10:5", 0, 0, 0, 0}, + {0x00300000, 0xffff8000, "adc.b", "r0:5,r5:5,r10:5", 0, 0, 0, 0}, + {0x00308000, 0xffff8000, "adc.h", "r0:5,r5:5,r10:5", 0, 0, 0, 0}, + {0x00310000, 0xffff8000, "adc.w", "r0:5,r5:5,r10:5", 0, 0, 0, 0}, + {0x00318000, 0xffff8000, "adc.d", "r0:5,r5:5,r10:5", 0, 0, 0, 0}, + {0x00320000, 0xffff8000, "sbc.b", "r0:5,r5:5,r10:5", 0, 0, 0, 0}, + {0x00328000, 0xffff8000, "sbc.h", "r0:5,r5:5,r10:5", 0, 0, 0, 0}, + {0x00330000, 0xffff8000, "sbc.w", "r0:5,r5:5,r10:5", 0, 0, 0, 0}, + {0x00338000, 0xffff8000, "sbc.d", "r0:5,r5:5,r10:5", 0, 0, 0, 0}, + {0x001a0000, 0xffff8000, "rotr.b", "r0:5,r5:5,r10:5", 0, 0, 0, 0}, + {0x001a8000, 0xffff8000, "rotr.h", "r0:5,r5:5,r10:5", 0, 0, 0, 0}, + {0x004c2000, 0xffffe000, "rotri.b", "r0:5,r5:5,u10:3", 0, 0, 0, 0}, + {0x004c4000, 0xffffc000, "rotri.h", "r0:5,r5:5,u10:4", 0, 0, 0, 0}, + {0x00340000, 0xffff8000, "rcr.b", "r0:5,r5:5,r10:5", 0, 0, 0, 0}, + {0x00348000, 0xffff8000, "rcr.h", "r0:5,r5:5,r10:5", 0, 0, 0, 0}, + {0x00350000, 0xffff8000, "rcr.w", "r0:5,r5:5,r10:5", 0, 0, 0, 0}, + {0x00358000, 0xffff8000, "rcr.d", "r0:5,r5:5,r10:5", 0, 0, 0, 0}, + {0x00502000, 0xffffe000, "rcri.b", "r0:5,r5:5,u10:3", 0, 0, 0, 0}, + {0x00504000, 0xffffc000, "rcri.h", "r0:5,r5:5,u10:4", 0, 0, 0, 0}, + {0x00508000, 0xffff8000, "rcri.w", "r0:5,r5:5,u10:5", 0, 0, 0, 0}, + {0x00510000, 0xffff0000, "rcri.d", "r0:5,r5:5,u10:6", 0, 0, 0, 0}, + {0x0114e400, 0xfffffc00, "fcvt.ud.d", "f0:5,f5:5", 0, 0, 0, 0}, + {0x0114e000, 0xfffffc00, "fcvt.ld.d", "f0:5,f5:5", 0, 0, 0, 0}, + {0x01150000, 0xffff8000, "fcvt.d.ld", "f0:5,f5:5,f10:5", 0, 0, 0, 0}, + {0x2e800000, 0xffc00000, "ldl.d", "r0:5,r5:5,s10:12", 0, 0, 0, 0}, + {0x2e000000, 0xffc00000, "ldl.w", "r0:5,r5:5,s10:12", 0, 0, 0, 0}, + {0x2e400000, 0xffc00000, "ldr.w", "r0:5,r5:5,s10:12", 0, 0, 0, 0}, + {0x2ec00000, 0xffc00000, "ldr.d", "r0:5,r5:5,s10:12", 0, 0, 0, 0}, + {0x2f000000, 0xffc00000, "stl.w", "r0:5,r5:5,s10:12", 0, 0, 0, 0}, + {0x2f800000, 0xffc00000, "stl.d", "r0:5,r5:5,s10:12", 0, 0, 0, 0}, + {0x2f400000, 0xffc00000, "str.w", "r0:5,r5:5,s10:12", 0, 0, 0, 0}, + {0x2fc00000, 0xffc00000, "str.d", "r0:5,r5:5,s10:12", 0, 0, 0, 0}, + {0x003f000c, 0xffff801f, "x86adc.b", "r5:5,r10:5", 0, 0, 0, 0}, + {0x003f000d, 0xffff801f, "x86adc.h", "r5:5,r10:5", 0, 0, 0, 0}, + {0x003f000e, 0xffff801f, "x86adc.w", "r5:5,r10:5", 0, 0, 0, 0}, + {0x003f000f, 0xffff801f, "x86adc.d", "r5:5,r10:5", 0, 0, 0, 0}, + {0x003f0004, 0xffff801f, "x86add.b", "r5:5,r10:5", 0, 0, 0, 0}, + {0x003f0005, 0xffff801f, "x86add.h", "r5:5,r10:5", 0, 0, 0, 0}, + {0x003f0006, 0xffff801f, "x86add.w", "r5:5,r10:5", 0, 0, 0, 0}, + {0x003f0007, 0xffff801f, "x86add.d", "r5:5,r10:5", 0, 0, 0, 0}, + {0x003f0000, 0xffff801f, "x86add.wu", "r5:5,r10:5", 0, 0, 0, 0}, + {0x003f0001, 0xffff801f, "x86add.du", "r5:5,r10:5", 0, 0, 0, 0}, + {0x00008000, 0xfffffc1f, "x86inc.b", "r5:5", 0, 0, 0, 0}, + {0x00008001, 0xfffffc1f, "x86inc.h", "r5:5", 0, 0, 0, 0}, + {0x00008002, 0xfffffc1f, "x86inc.w", "r5:5", 0, 0, 0, 0}, + {0x00008003, 0xfffffc1f, "x86inc.d", "r5:5", 0, 0, 0, 0}, + {0x003f0010, 0xffff801f, "x86sbc.b", "r5:5,r10:5", 0, 0, 0, 0}, + {0x003f0011, 0xffff801f, "x86sbc.h", "r5:5,r10:5", 0, 0, 0, 0}, + {0x003f0012, 0xffff801f, "x86sbc.w", "r5:5,r10:5", 0, 0, 0, 0}, + {0x003f0013, 0xffff801f, "x86sbc.d", "r5:5,r10:5", 0, 0, 0, 0}, + {0x003f0008, 0xffff801f, "x86sub.b", "r5:5,r10:5", 0, 0, 0, 0}, + {0x003f0009, 0xffff801f, "x86sub.h", "r5:5,r10:5", 0, 0, 0, 0}, + {0x003f000a, 0xffff801f, "x86sub.w", "r5:5,r10:5", 0, 0, 0, 0}, + {0x003f000b, 0xffff801f, "x86sub.d", "r5:5,r10:5", 0, 0, 0, 0}, + {0x003f0002, 0xffff801f, "x86sub.wu", "r5:5,r10:5", 0, 0, 0, 0}, + {0x003f0003, 0xffff801f, "x86sub.du", "r5:5,r10:5", 0, 0, 0, 0}, + {0x00008004, 0xfffffc1f, "x86dec.b", "r5:5", 0, 0, 0, 0}, + {0x00008005, 0xfffffc1f, "x86dec.h", "r5:5", 0, 0, 0, 0}, + {0x00008006, 0xfffffc1f, "x86dec.w", "r5:5", 0, 0, 0, 0}, + {0x00008007, 0xfffffc1f, "x86dec.d", "r5:5", 0, 0, 0, 0}, + {0x003f8010, 0xffff801f, "x86and.b", "r5:5,r10:5", 0, 0, 0, 0}, + {0x003f8011, 0xffff801f, "x86and.h", "r5:5,r10:5", 0, 0, 0, 0}, + {0x003f8012, 0xffff801f, "x86and.w", "r5:5,r10:5", 0, 0, 0, 0}, + {0x003f8013, 0xffff801f, "x86and.d", "r5:5,r10:5", 0, 0, 0, 0}, + {0x003f8014, 0xffff801f, "x86or.b", "r5:5,r10:5", 0, 0, 0, 0}, + {0x003f8015, 0xffff801f, "x86or.h", "r5:5,r10:5", 0, 0, 0, 0}, + {0x003f8016, 0xffff801f, "x86or.w", "r5:5,r10:5", 0, 0, 0, 0}, + {0x003f8017, 0xffff801f, "x86or.d", "r5:5,r10:5", 0, 0, 0, 0}, + {0x003f8018, 0xffff801f, "x86xor.b", "r5:5,r10:5", 0, 0, 0, 0}, + {0x003f8019, 0xffff801f, "x86xor.h", "r5:5,r10:5", 0, 0, 0, 0}, + {0x003f801a, 0xffff801f, "x86xor.w", "r5:5,r10:5", 0, 0, 0, 0}, + {0x003f801b, 0xffff801f, "x86xor.d", "r5:5,r10:5", 0, 0, 0, 0}, + {0x003e8000, 0xffff801f, "x86mul.b", "r5:5,r10:5", 0, 0, 0, 0}, + {0x003e8001, 0xffff801f, "x86mul.h", "r5:5,r10:5", 0, 0, 0, 0}, + {0x003e8002, 0xffff801f, "x86mul.w", "r5:5,r10:5", 0, 0, 0, 0}, + {0x003e8003, 0xffff801f, "x86mul.d", "r5:5,r10:5", 0, 0, 0, 0}, + {0x003e8004, 0xffff801f, "x86mul.bu", "r5:5,r10:5", 0, 0, 0, 0}, + {0x003e8005, 0xffff801f, "x86mul.hu", "r5:5,r10:5", 0, 0, 0, 0}, + {0x003e8006, 0xffff801f, "x86mul.wu", "r5:5,r10:5", 0, 0, 0, 0}, + {0x003e8007, 0xffff801f, "x86mul.du", "r5:5,r10:5", 0, 0, 0, 0}, + {0x003f800c, 0xffff801f, "x86rcl.b", "r5:5,r10:5", 0, 0, 0, 0}, + {0x003f800d, 0xffff801f, "x86rcl.h", "r5:5,r10:5", 0, 0, 0, 0}, + {0x003f800e, 0xffff801f, "x86rcl.w", "r5:5,r10:5", 0, 0, 0, 0}, + {0x003f800f, 0xffff801f, "x86rcl.d", "r5:5,r10:5", 0, 0, 0, 0}, + {0x00542018, 0xffffe01f, "x86rcli.b", "r5:5,u10:3", 0, 0, 0, 0}, + {0x00544019, 0xffffc01f, "x86rcli.h", "r5:5,u10:4", 0, 0, 0, 0}, + {0x0054801a, 0xffff801f, "x86rcli.w", "r5:5,u10:5", 0, 0, 0, 0}, + {0x0055001b, 0xffff001f, "x86rcli.d", "r5:5,u10:6", 0, 0, 0, 0}, + {0x003f8008, 0xffff801f, "x86rcr.b", "r5:5,r10:5", 0, 0, 0, 0}, + {0x003f8009, 0xffff801f, "x86rcr.h", "r5:5,r10:5", 0, 0, 0, 0}, + {0x003f800a, 0xffff801f, "x86rcr.w", "r5:5,r10:5", 0, 0, 0, 0}, + {0x003f800b, 0xffff801f, "x86rcr.d", "r5:5,r10:5", 0, 0, 0, 0}, + {0x00542010, 0xffffe01f, "x86rcri.b", "r5:5,u10:3", 0, 0, 0, 0}, + {0x00544011, 0xffffc01f, "x86rcri.h", "r5:5,u10:4", 0, 0, 0, 0}, + {0x00548012, 0xffff801f, "x86rcri.w", "r5:5,u10:5", 0, 0, 0, 0}, + {0x00550013, 0xffff001f, "x86rcri.d", "r5:5,u10:6", 0, 0, 0, 0}, + {0x003f8004, 0xffff801f, "x86rotl.b", "r5:5,r10:5", 0, 0, 0, 0}, + {0x003f8005, 0xffff801f, "x86rotl.h", "r5:5,r10:5", 0, 0, 0, 0}, + {0x003f8006, 0xffff801f, "x86rotl.w", "r5:5,r10:5", 0, 0, 0, 0}, + {0x003f8007, 0xffff801f, "x86rotl.d", "r5:5,r10:5", 0, 0, 0, 0}, + {0x00542014, 0xffffe01f, "x86rotli.b", "r5:5,u10:3", 0, 0, 0, 0}, + {0x00544015, 0xffffc01f, "x86rotli.h", "r5:5,u10:4", 0, 0, 0, 0}, + {0x00548016, 0xffff801f, "x86rotli.w", "r5:5,u10:5", 0, 0, 0, 0}, + {0x00550017, 0xffff001f, "x86rotli.d", "r5:5,u10:6", 0, 0, 0, 0}, + {0x003f8000, 0xffff801f, "x86rotr.b", "r5:5,r10:5", 0, 0, 0, 0}, + {0x003f8001, 0xffff801f, "x86rotr.h", "r5:5,r10:5", 0, 0, 0, 0}, + {0x003f8002, 0xffff801f, "x86rotr.d", "r5:5,r10:5", 0, 0, 0, 0}, + {0x003f8003, 0xffff801f, "x86rotr.w", "r5:5,r10:5", 0, 0, 0, 0}, + {0x0054200c, 0xffffe01f, "x86rotri.b", "r5:5,u10:3", 0, 0, 0, 0}, + {0x0054400d, 0xffffc01f, "x86rotri.h", "r5:5,u10:4", 0, 0, 0, 0}, + {0x0054800e, 0xffff801f, "x86rotri.w", "r5:5,u10:5", 0, 0, 0, 0}, + {0x0055000f, 0xffff001f, "x86rotri.d", "r5:5,u10:6", 0, 0, 0, 0}, + {0x003f0014, 0xffff801f, "x86sll.b", "r5:5,r10:5", 0, 0, 0, 0}, + {0x003f0015, 0xffff801f, "x86sll.h", "r5:5,r10:5", 0, 0, 0, 0}, + {0x003f0016, 0xffff801f, "x86sll.w", "r5:5,r10:5", 0, 0, 0, 0}, + {0x003f0017, 0xffff801f, "x86sll.d", "r5:5,r10:5", 0, 0, 0, 0}, + {0x00542000, 0xffffe01f, "x86slli.b", "r5:5,u10:3", 0, 0, 0, 0}, + {0x00544001, 0xffffc01f, "x86slli.h", "r5:5,u10:4", 0, 0, 0, 0}, + {0x00548002, 0xffff801f, "x86slli.w", "r5:5,u10:5", 0, 0, 0, 0}, + {0x00550003, 0xffff001f, "x86slli.d", "r5:5,u10:6", 0, 0, 0, 0}, + {0x003f0018, 0xffff801f, "x86srl.b", "r5:5,r10:5", 0, 0, 0, 0}, + {0x003f0019, 0xffff801f, "x86srl.h", "r5:5,r10:5", 0, 0, 0, 0}, + {0x003f001a, 0xffff801f, "x86srl.w", "r5:5,r10:5", 0, 0, 0, 0}, + {0x003f001b, 0xffff801f, "x86srl.d", "r5:5,r10:5", 0, 0, 0, 0}, + {0x00542004, 0xffffe01f, "x86srli.b", "r5:5,u10:3", 0, 0, 0, 0}, + {0x00544005, 0xffffc01f, "x86srli.h", "r5:5,u10:4", 0, 0, 0, 0}, + {0x00548006, 0xffff801f, "x86srli.w", "r5:5,u10:5", 0, 0, 0, 0}, + {0x00550007, 0xffff001f, "x86srli.d", "r5:5,u10:6", 0, 0, 0, 0}, + {0x003f001c, 0xffff801f, "x86sra.b", "r5:5,r10:5", 0, 0, 0, 0}, + {0x003f001d, 0xffff801f, "x86sra.h", "r5:5,r10:5", 0, 0, 0, 0}, + {0x003f001e, 0xffff801f, "x86sra.w", "r5:5,r10:5", 0, 0, 0, 0}, + {0x003f001f, 0xffff801f, "x86sra.d", "r5:5,r10:5", 0, 0, 0, 0}, + {0x00542008, 0xffffe01f, "x86srai.b", "r5:5,u10:3", 0, 0, 0, 0}, + {0x00544009, 0xffffc01f, "x86srai.h", "r5:5,u10:4", 0, 0, 0, 0}, + {0x0054800a, 0xffff801f, "x86srai.w", "r5:5,u10:5", 0, 0, 0, 0}, + {0x0055000b, 0xffff001f, "x86srai.d", "r5:5,u10:6", 0, 0, 0, 0}, + {0x00368000, 0xffffc3e0, "setx86j", "r0:5,u10:4", 0, 0, 0, 0}, + {0x00007800, 0xfffffc00, "setx86loope", "r0:5,r5:5", 0, 0, 0, 0}, + {0x00007c00, 0xfffffc00, "setx86loopne", "r0:5,r5:5", 0, 0, 0, 0}, + {0x005c0000, 0xfffc03e0, "x86mfflag", "r0:5,u10:8", 0, 0, 0, 0}, + {0x005c0020, 0xfffc03e0, "x86mtflag", "r0:5,u10:8", 0, 0, 0, 0}, + {0x00007400, 0xffffffe0, "x86mftop", "r0:5", 0, 0, 0, 0}, + {0x00007000, 0xffffff1f, "x86mttop", "u5:3", 0, 0, 0, 0}, + {0x00008009, 0xffffffff, "x86inctop", "", 0, 0, 0, 0}, + {0x00008029, 0xffffffff, "x86dectop", "", 0, 0, 0, 0}, + {0x00008008, 0xffffffff, "x86settm", "", 0, 0, 0, 0}, + {0x00008028, 0xffffffff, "x86clrtm", "", 0, 0, 0, 0}, + {0x00580000, 0xfffc0000, "x86settag", "r0:5,u5:5,u10:8", 0, 0, 0, 0}, + {0x00370010, 0xffff8010, "armadd.w", "r5:5,r10:5,u0:4", 0, 0, 0, 0}, + {0x00378010, 0xffff8010, "armsub.w", "r5:5,r10:5,u0:4", 0, 0, 0, 0}, + {0x00380010, 0xffff8010, "armadc.w", "r5:5,r10:5,u0:4", 0, 0, 0, 0}, + {0x00388010, 0xffff8010, "armsbc.w", "r5:5,r10:5,u0:4", 0, 0, 0, 0}, + {0x00390010, 0xffff8010, "armand.w", "r5:5,r10:5,u0:4", 0, 0, 0, 0}, + {0x00398010, 0xffff8010, "armor.w", "r5:5,r10:5,u0:4", 0, 0, 0, 0}, + {0x003a0010, 0xffff8010, "armxor.w", "r5:5,r10:5,u0:4", 0, 0, 0, 0}, + {0x003fc01c, 0xffffc01f, "armnot.w", "r5:5,u10:4", 0, 0, 0, 0}, + {0x003a8010, 0xffff8010, "armsll.w", "r5:5,r10:5,u0:4", 0, 0, 0, 0}, + {0x003b0010, 0xffff8010, "armsrl.w", "r5:5,r10:5,u0:4", 0, 0, 0, 0}, + {0x003b8010, 0xffff8010, "armsra.w", "r5:5,r10:5,u0:4", 0, 0, 0, 0}, + {0x003c0010, 0xffff8010, "armrotr.w", "r5:5,r10:5,u0:4", 0, 0, 0, 0}, + {0x003c8010, 0xffff8010, "armslli.w", "r5:5,u10:5,u0:4", 0, 0, 0, 0}, + {0x003d0010, 0xffff8010, "armsrli.w", "r5:5,u10:5,u0:4", 0, 0, 0, 0}, + {0x003d8010, 0xffff8010, "armsrai.w", "r5:5,u10:5,u0:4", 0, 0, 0, 0}, + {0x003e0010, 0xffff8010, "armrotri.w", "r5:5,u10:5,u0:4", 0, 0, 0, 0}, + {0x003fc01f, 0xffffc01f, "armrrx.w", "r5:5,u10:4", 0, 0, 0, 0}, + {0x00364000, 0xffffc000, "armmove", "r0:5,r5:5,u10:4", 0, 0, 0, 0}, + {0x003fc01d, 0xffffc01f, "armmov.w", "r5:5,u10:4", 0, 0, 0, 0}, + {0x003fc01e, 0xffffc01f, "armmov.d", "r5:5,u10:4", 0, 0, 0, 0}, + {0x005c0040, 0xfffc03e0, "armmfflag", "r0:5,u10:8", 0, 0, 0, 0}, + {0x005c0060, 0xfffc03e0, "armmtflag", "r0:5,u10:8", 0, 0, 0, 0}, + {0x0036c000, 0xffffc3e0, "setarmj", "r0:5,u10:4", 0, 0, 0, 0}, + { 0, 0, 0, 0, 0, 0, 0, 0 } /* Terminate the list. */ }; struct loongarch_ase loongarch_ASEs[] = { { &LARCH_opts.ase_ilp32, loongarch_macro_opcodes, 0, 0, { 0 }, 0, 0 }, + { &LARCH_opts.ase_ilp32, loongarch_alias_opcodes, 0, 0, { 0 }, 0, 0 }, { &LARCH_opts.ase_ilp32, loongarch_imm_opcodes, 0, 0, { 0 }, 0, 0 }, { &LARCH_opts.ase_ilp32, loongarch_privilege_opcodes, 0, 0, { 0 }, 0, 0 }, { &LARCH_opts.ase_ilp32, loongarch_load_store_opcodes, 0, 0, { 0 }, 0, 0 }, @@ -866,5 +2549,9 @@ struct loongarch_ase loongarch_ASEs[] = { &LARCH_opts.ase_df, loongarch_4opt_double_float_opcodes, 0, 0, { 0 }, 0, 0 }, { &LARCH_opts.ase_sf, loongarch_single_float_load_store_opcodes, 0, 0, { 0 }, 0, 0 }, { &LARCH_opts.ase_df, loongarch_double_float_load_store_opcodes, 0, 0, { 0 }, 0, 0 }, + { &LARCH_opts.ase_lsx, loongarch_lsx_opcodes, 0, 0, { 0 }, 0, 0 }, + { &LARCH_opts.ase_lasx, loongarch_lasx_opcodes, 0, 0, { 0 }, 0, 0 }, + { &LARCH_opts.ase_lvz, loongarch_lvz_opcodes, 0, 0, { 0 }, 0, 0 }, + { &LARCH_opts.ase_lbt, loongarch_lbt_opcodes, 0, 0, { 0 }, 0, 0 }, { 0 }, }; -- 2.33.0
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